From patchwork Sat Mar 9 18:11:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 226358 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id BFDD22C0344 for ; Sun, 10 Mar 2013 05:13:48 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751133Ab3CISNh (ORCPT ); Sat, 9 Mar 2013 13:13:37 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:5073 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750804Ab3CISNV (ORCPT ); Sat, 9 Mar 2013 13:13:21 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Sat, 09 Mar 2013 10:13:11 -0800 Received: from hqemhub03.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Sat, 09 Mar 2013 10:06:58 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Sat, 09 Mar 2013 10:06:58 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.298.1; Sat, 9 Mar 2013 10:13:15 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Sat, 09 Mar 2013 10:13:15 -0800 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r29ID1sg027049; Sat, 9 Mar 2013 10:13:13 -0800 (PST) From: Laxman Dewangan To: CC: , , , , Laxman Dewangan Subject: [PATCH V2 5/5] ARM: DT: tegra114: Add spi controller DT entry Date: Sat, 9 Mar 2013 23:41:18 +0530 Message-ID: <1362852678-13421-6-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1362852678-13421-1-git-send-email-ldewangan@nvidia.com> References: <1362852678-13421-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org NVIDIA's Tegra114 has 6 spi controllers. These controllers are redesign on T114 with different register interface. Add DT entry for spi controllers and make it compatible with "nvidia,tegra114-spi". Signed-off-by: Laxman Dewangan --- Changes from V1: - None arch/arm/boot/dts/tegra114.dtsi | 72 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 72 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 21ff340..47ad1b8 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -209,6 +209,78 @@ clock-names = "div-clk"; }; + spi@7000d400 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d400 0x200>; + interrupts = <0 59 0x04>; + nvidia,dma-request-selector = <&apbdma 15>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 41>; + clock-names = "spi"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 44>; + clock-names = "spi"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d480 0x200>; + interrupts = <0 83 0x04>; + nvidia,dma-request-selector = <&apbdma 17>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 46>; + clock-names = "spi"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000da00 0x200>; + interrupts = <0 93 0x04>; + nvidia,dma-request-selector = <&apbdma 18>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 68>; + clock-names = "spi"; + status = "disabled"; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000dc00 0x200>; + interrupts = <0 94 0x04>; + nvidia,dma-request-selector = <&apbdma 27>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 104>; + clock-names = "spi"; + status = "disabled"; + }; + + spi@7000de00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000de00 0x200>; + interrupts = <0 79 0x04>; + nvidia,dma-request-selector = <&apbdma 28>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car 105>; + clock-names = "spi"; + status = "disabled"; + }; + sdhci@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>;