Patchwork [1/5] ARM: DT: tegra114: add APB DMA controller DT entry

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Submitter Laxman Dewangan
Date March 8, 2013, 1:52 p.m.
Message ID <1362750782-15174-2-git-send-email-ldewangan@nvidia.com>
Download mbox | patch
Permalink /patch/226126/
State Superseded, archived
Headers show

Comments

Laxman Dewangan - March 8, 2013, 1:52 p.m.
NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 arch/arm/boot/dts/tegra114.dtsi |   38 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)
Stephen Warren - March 8, 2013, 5:51 p.m.
On 03/08/2013 06:52 AM, Laxman Dewangan wrote:
> NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
> APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".

> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi

> +	apbdma: dma {
> +		compatible = "nvidia,tegra114-apbdma";

So I know that the Tegra114 HW has a new channel-pause feature, which
the driver /can/ use. However, if the driver didn't know about that
feature, and continued to use the global-pause feature, would it still
work fine?

In other words, is the Tegra114 HW 100% backwards-compatible with the
Tegra30 HW, it's just that there are new features that SW could
optionally use?

If that is true, then we should also include "nvidia,tegra30-apbdma" in
the compatible value.
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Laxman Dewangan - March 8, 2013, 6:06 p.m.
On Friday 08 March 2013 11:21 PM, Stephen Warren wrote:
> On 03/08/2013 06:52 AM, Laxman Dewangan wrote:
>> NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
>> APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".
>> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
>> +	apbdma: dma {
>> +		compatible = "nvidia,tegra114-apbdma";
> So I know that the Tegra114 HW has a new channel-pause feature, which
> the driver /can/ use. However, if the driver didn't know about that
> feature, and continued to use the global-pause feature, would it still
> work fine?
>
> In other words, is the Tegra114 HW 100% backwards-compatible with the
> Tegra30 HW, it's just that there are new features that SW could
> optionally use?
>
> If that is true, then we should also include "nvidia,tegra30-apbdma" in
> the compatible value.

Tegra114 HW is not compatible with the tegra30 as with global pause, it 
is not able to write into the dma register in T114. On t114, the dma 
register is clock gated with global enable/disable.



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Stephen Warren - March 8, 2013, 6:41 p.m.
On 03/08/2013 11:06 AM, Laxman Dewangan wrote:
> On Friday 08 March 2013 11:21 PM, Stephen Warren wrote:
>> On 03/08/2013 06:52 AM, Laxman Dewangan wrote:
>>> NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
>>> APB DMA controllers and make it compatible with
>>> "nvidia,tegra114-apbdma".
>>> diff --git a/arch/arm/boot/dts/tegra114.dtsi
>>> b/arch/arm/boot/dts/tegra114.dtsi
>>> +    apbdma: dma {
>>> +        compatible = "nvidia,tegra114-apbdma";
>> So I know that the Tegra114 HW has a new channel-pause feature, which
>> the driver /can/ use. However, if the driver didn't know about that
>> feature, and continued to use the global-pause feature, would it still
>> work fine?
>>
>> In other words, is the Tegra114 HW 100% backwards-compatible with the
>> Tegra30 HW, it's just that there are new features that SW could
>> optionally use?
>>
>> If that is true, then we should also include "nvidia,tegra30-apbdma" in
>> the compatible value.
> 
> Tegra114 HW is not compatible with the tegra30 as with global pause, it
> is not able to write into the dma register in T114. On t114, the dma
> register is clock gated with global enable/disable.

Interesting. In that case, the compatible value above is entirely
correct. Thanks for the explanation. It might be worth mentioning this
in the commit description.

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Laxman Dewangan - March 8, 2013, 6:46 p.m.
On Saturday 09 March 2013 12:11 AM, Stephen Warren wrote:
> On 03/08/2013 11:06 AM, Laxman Dewangan wrote:
>> On Friday 08 March 2013 11:21 PM, Stephen Warren wrote:
>>> On 03/08/2013 06:52 AM, Laxman Dewangan wrote:
>>>> NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
>>>> APB DMA controllers and make it compatible with
>>>> "nvidia,tegra114-apbdma".
>>>> diff --git a/arch/arm/boot/dts/tegra114.dtsi
>>>> b/arch/arm/boot/dts/tegra114.dtsi
>>>> +    apbdma: dma {
>>>> +        compatible = "nvidia,tegra114-apbdma";
>>> So I know that the Tegra114 HW has a new channel-pause feature, which
>>> the driver /can/ use. However, if the driver didn't know about that
>>> feature, and continued to use the global-pause feature, would it still
>>> work fine?
>>>
>>> In other words, is the Tegra114 HW 100% backwards-compatible with the
>>> Tegra30 HW, it's just that there are new features that SW could
>>> optionally use?
>>>
>>> If that is true, then we should also include "nvidia,tegra30-apbdma" in
>>> the compatible value.
>> Tegra114 HW is not compatible with the tegra30 as with global pause, it
>> is not able to write into the dma register in T114. On t114, the dma
>> register is clock gated with global enable/disable.
> Interesting. In that case, the compatible value above is entirely
> correct. Thanks for the explanation. It might be worth mentioning this
> in the commit description.

I can describe here as I am going to respin the patches anyhow.
However, I have already explain this in the driver commit when porting 
for T114.


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Patch

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 0eec49f..b73b8a6 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -38,6 +38,44 @@ 
 		reg = <0x6000c004 0x14c>;
 	};
 
+	apbdma: dma {
+		compatible = "nvidia,tegra114-apbdma";
+		reg = <0x6000a000 0x1400>;
+		interrupts = <0 104 0x04
+			      0 105 0x04
+			      0 106 0x04
+			      0 107 0x04
+			      0 108 0x04
+			      0 109 0x04
+			      0 110 0x04
+			      0 111 0x04
+			      0 112 0x04
+			      0 113 0x04
+			      0 114 0x04
+			      0 115 0x04
+			      0 116 0x04
+			      0 117 0x04
+			      0 118 0x04
+			      0 119 0x04
+			      0 128 0x04
+			      0 129 0x04
+			      0 130 0x04
+			      0 131 0x04
+			      0 132 0x04
+			      0 133 0x04
+			      0 134 0x04
+			      0 135 0x04
+			      0 136 0x04
+			      0 137 0x04
+			      0 138 0x04
+			      0 139 0x04
+			      0 140 0x04
+			      0 141 0x04
+			      0 142 0x04
+			      0 143 0x04>;
+		clocks = <&tegra_car 34>;
+	};
+
 	gpio: gpio {
 		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;