From patchwork Fri Mar 8 13:53:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 226124 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6C67B2C03B8 for ; Sat, 9 Mar 2013 00:55:59 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758117Ab3CHNzD (ORCPT ); Fri, 8 Mar 2013 08:55:03 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:11797 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758107Ab3CHNy7 (ORCPT ); Fri, 8 Mar 2013 08:54:59 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Fri, 08 Mar 2013 06:00:03 -0800 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 08 Mar 2013 05:54:55 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 08 Mar 2013 05:54:55 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.298.1; Fri, 8 Mar 2013 05:54:55 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 08 Mar 2013 05:54:55 -0800 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r28DsjCO003123; Fri, 8 Mar 2013 05:54:53 -0800 (PST) From: Laxman Dewangan To: CC: , , , , Laxman Dewangan Subject: [PATCH 3/5] ARM: DT: tegra114:add aliases and DMA requestor for serial controller Date: Fri, 8 Mar 2013 19:23:00 +0530 Message-ID: <1362750782-15174-4-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1362750782-15174-1-git-send-email-ldewangan@nvidia.com> References: <1362750782-15174-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra30-hsuart. Also Fix the clock id for the UARTB. Signed-off-by: Laxman Dewangan --- arch/arm/boot/dts/tegra114.dtsi | 29 ++++++++++++++++++++++++----- 1 files changed, 24 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 14afbc8..686e33f 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -4,6 +4,13 @@ compatible = "nvidia,tegra114"; interrupt-parent = <&gic>; + aliases { + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartc; + serial3 = &uartd; + }; + gic: interrupt-controller { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; @@ -99,38 +106,50 @@ 0x70003000 0x40c>; /* Mux registers */ }; - serial@70006000 { + /* + * There are two serial driver i.e. 8250 based simple serial + * driver and APB DMA based serial driver for higher baudrate + * and performace. To enable the 8250 based driver, the compatible + * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable + * the APB DMA based serial driver, the comptible is + * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". + */ + uarta: serial@70006000 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <0 36 0x04>; + nvidia,dma-request-selector = <&apbdma 8>; status = "disabled"; clocks = <&tegra_car 6>; }; - serial@70006040 { + uartb: serial@70006040 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <0 37 0x04>; + nvidia,dma-request-selector = <&apbdma 9>; status = "disabled"; - clocks = <&tegra_car 192>; + clocks = <&tegra_car 7>; }; - serial@70006200 { + uartc: serial@70006200 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <0 46 0x04>; + nvidia,dma-request-selector = <&apbdma 10>; status = "disabled"; clocks = <&tegra_car 55>; }; - serial@70006300 { + uartd: serial@70006300 { compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <0 90 0x04>; + nvidia,dma-request-selector = <&apbdma 19>; status = "disabled"; clocks = <&tegra_car 65>; };