From patchwork Fri Mar 8 13:53:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 226123 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id AC55E2C035F for ; Sat, 9 Mar 2013 00:55:39 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934184Ab3CHNzM (ORCPT ); Fri, 8 Mar 2013 08:55:12 -0500 Received: from hqemgate04.nvidia.com ([216.228.121.35]:9922 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934169Ab3CHNzK (ORCPT ); Fri, 8 Mar 2013 08:55:10 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Fri, 08 Mar 2013 05:54:53 -0800 Received: from hqemhub03.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 08 Mar 2013 05:48:46 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 08 Mar 2013 05:48:46 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.298.1; Fri, 8 Mar 2013 05:54:57 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 08 Mar 2013 05:54:57 -0800 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r28DsjCP003123; Fri, 8 Mar 2013 05:54:55 -0800 (PST) From: Laxman Dewangan To: CC: , , , , Laxman Dewangan Subject: [PATCH 4/5] ARM: DT: tegra114: add KBC controller DT entry Date: Fri, 8 Mar 2013 19:23:01 +0530 Message-ID: <1362750782-15174-5-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1362750782-15174-1-git-send-email-ldewangan@nvidia.com> References: <1362750782-15174-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org NVIDIA's Tegra114 SoCs have the matrix keyboard controller which supports 11x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan --- arch/arm/boot/dts/tegra114.dtsi | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 686e33f..18fbd49 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -248,6 +248,14 @@ clocks = <&tegra_car 4>; }; + kbc { + compatible = "nvidia,tegra20-kbc"; + reg = <0x7000e200 0x100>; + interrupts = <0 85 0x04>; + clocks = <&tegra_car 36>; + status = "disabled"; + }; + pmc { compatible = "nvidia,tegra114-pmc"; reg = <0x7000e400 0x400>;