Patchwork [1/1] clk: tegra: Fix periph_clk_to_bit macro

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Submitter achew@nvidia.com
Date March 6, 2013, 9:47 p.m.
Message ID <1362606444-19970-1-git-send-email-achew@nvidia.com>
Download mbox | patch
Permalink /patch/225655/
State Accepted, archived
Headers show

Comments

achew@nvidia.com - March 6, 2013, 9:47 p.m.
The parameter name should be "gate", not "periph".  This worked, however,
because it happens that everywhere periph_clk_to_bit is called, "gate" was
in the local scope.

Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Andrew Chew <achew@nvidia.com>
---
 drivers/clk/tegra/clk-periph-gate.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Stephen Warren - March 6, 2013, 9:59 p.m.
On 03/06/2013 02:47 PM, Andrew Chew wrote:
> The parameter name should be "gate", not "periph".  This worked, however,
> because it happens that everywhere periph_clk_to_bit is called, "gate" was
> in the local scope.

Peter, Prashant, can I get an ack/reviewed-by please?

Note: I'm also CC'ing Mike and the LAKML mailing list; common clock
driver changes should be sent to Mike as CCF maintainer, and any
ARM-related changes should typically get sent to LAKML in the absence of
any other specific subsystem list.

> Signed-off-by: Yen Lin <yelin@nvidia.com>
> Signed-off-by: Andrew Chew <achew@nvidia.com>
> ---
>  drivers/clk/tegra/clk-periph-gate.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
> index 6dd5332..d87e1ce 100644
> --- a/drivers/clk/tegra/clk-periph-gate.c
> +++ b/drivers/clk/tegra/clk-periph-gate.c
> @@ -41,7 +41,7 @@ static DEFINE_SPINLOCK(periph_ref_lock);
>  #define write_rst_clr(val, gate) \
>  	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
>  
> -#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
> +#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
>  
>  /* Peripheral gate clock ops */
>  static int clk_periph_is_enabled(struct clk_hw *hw)

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Thierry Reding - March 7, 2013, 7:02 a.m.
On Wed, Mar 06, 2013 at 01:47:24PM -0800, Andrew Chew wrote:
> The parameter name should be "gate", not "periph".  This worked, however,
> because it happens that everywhere periph_clk_to_bit is called, "gate" was
> in the local scope.
> 
> Signed-off-by: Yen Lin <yelin@nvidia.com>
> Signed-off-by: Andrew Chew <achew@nvidia.com>
> ---
>  drivers/clk/tegra/clk-periph-gate.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
> index 6dd5332..d87e1ce 100644
> --- a/drivers/clk/tegra/clk-periph-gate.c
> +++ b/drivers/clk/tegra/clk-periph-gate.c
> @@ -41,7 +41,7 @@ static DEFINE_SPINLOCK(periph_ref_lock);
>  #define write_rst_clr(val, gate) \
>  	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
>  
> -#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
> +#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
>  
>  /* Peripheral gate clock ops */
>  static int clk_periph_is_enabled(struct clk_hw *hw)

Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Prashant Gaikwad - March 7, 2013, 9:35 a.m.
On Thursday 07 March 2013 03:29 AM, Stephen Warren wrote:
> On 03/06/2013 02:47 PM, Andrew Chew wrote:
>> The parameter name should be "gate", not "periph".  This worked, however,
>> because it happens that everywhere periph_clk_to_bit is called, "gate" was
>> in the local scope.
> Peter, Prashant, can I get an ack/reviewed-by please?

Thanks for the fix!!

Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>

> Note: I'm also CC'ing Mike and the LAKML mailing list; common clock
> driver changes should be sent to Mike as CCF maintainer, and any
> ARM-related changes should typically get sent to LAKML in the absence of
> any other specific subsystem list.
>
>> Signed-off-by: Yen Lin <yelin@nvidia.com>
>> Signed-off-by: Andrew Chew <achew@nvidia.com>
>> ---
>>   drivers/clk/tegra/clk-periph-gate.c |    2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
>> index 6dd5332..d87e1ce 100644
>> --- a/drivers/clk/tegra/clk-periph-gate.c
>> +++ b/drivers/clk/tegra/clk-periph-gate.c
>> @@ -41,7 +41,7 @@ static DEFINE_SPINLOCK(periph_ref_lock);
>>   #define write_rst_clr(val, gate) \
>>   	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
>>   
>> -#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
>> +#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
>>   
>>   /* Peripheral gate clock ops */
>>   static int clk_periph_is_enabled(struct clk_hw *hw)
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Peter De Schrijver - March 11, 2013, 9:09 a.m.
On Wed, Mar 06, 2013 at 10:47:24PM +0100, Andrew Chew wrote:
> The parameter name should be "gate", not "periph".  This worked, however,
> because it happens that everywhere periph_clk_to_bit is called, "gate" was
> in the local scope.
> 
> Signed-off-by: Yen Lin <yelin@nvidia.com>
> Signed-off-by: Andrew Chew <achew@nvidia.com>

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>

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Stephen Warren - March 21, 2013, 7:59 p.m.
On 03/06/2013 02:47 PM, Andrew Chew wrote:
> The parameter name should be "gate", not "periph".  This worked, however,
> because it happens that everywhere periph_clk_to_bit is called, "gate" was
> in the local scope.

Mike, could you please ack this so that I can take it through the Tegra
tree with the rest of the Tegra clock changes for 3.10? Thanks.

Oh, I see this was never sent to Mike:-( Hence, I'm quoting the whole patch.

> Signed-off-by: Yen Lin <yelin@nvidia.com>
> Signed-off-by: Andrew Chew <achew@nvidia.com>
> ---
>  drivers/clk/tegra/clk-periph-gate.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
> index 6dd5332..d87e1ce 100644
> --- a/drivers/clk/tegra/clk-periph-gate.c
> +++ b/drivers/clk/tegra/clk-periph-gate.c
> @@ -41,7 +41,7 @@ static DEFINE_SPINLOCK(periph_ref_lock);
>  #define write_rst_clr(val, gate) \
>  	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
>  
> -#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
> +#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
>  
>  /* Peripheral gate clock ops */
>  static int clk_periph_is_enabled(struct clk_hw *hw)
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Stephen Warren - March 22, 2013, 6:43 p.m.
On 03/21/2013 03:25 PM, Mike Turquette wrote:
> Quoting Stephen Warren (2013-03-21 12:59:29)
>> On 03/06/2013 02:47 PM, Andrew Chew wrote:
>>> The parameter name should be "gate", not "periph".  This worked, however,
>>> because it happens that everywhere periph_clk_to_bit is called, "gate" was
>>> in the local scope.
>>
>> Mike, could you please ack this so that I can take it through the Tegra
>> tree with the rest of the Tegra clock changes for 3.10? Thanks.
>>
>> Oh, I see this was never sent to Mike:-( Hence, I'm quoting the whole patch.
>>
> 
> Thanks for looping me in to the original patch.
> 
> I'm still going through v7 of the tegra114 patches now, so acking this
> is is a bit out-of-sequence, but the change is trivial enough:
> 
> Acked-by: Mike Turquette <mturquette@linaro.org>

Thanks.

This is actually a fix for the previous existing clock drivers for
Tegra20 and Tegra30, so I'll apply it before the Tegra114 CCF series.

Applied to Tegra's for-3.10/clk branch.
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Patch

diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 6dd5332..d87e1ce 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -41,7 +41,7 @@  static DEFINE_SPINLOCK(periph_ref_lock);
 #define write_rst_clr(val, gate) \
 	writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
 
-#define periph_clk_to_bit(periph) (1 << (gate->clk_num % 32))
+#define periph_clk_to_bit(gate) (1 << (gate->clk_num % 32))
 
 /* Peripheral gate clock ops */
 static int clk_periph_is_enabled(struct clk_hw *hw)