From patchwork Wed Mar 6 03:44:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 225292 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5C3162C0378 for ; Wed, 6 Mar 2013 15:03:55 +1100 (EST) Received: from localhost ([::1]:49358 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UD5a5-0001Ea-I1 for incoming@patchwork.ozlabs.org; Tue, 05 Mar 2013 23:03:53 -0500 Received: from eggs.gnu.org ([208.118.235.92]:51571) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UD5IC-0004EA-DQ for qemu-devel@nongnu.org; Tue, 05 Mar 2013 22:45:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UD5Hh-0007tD-HG for qemu-devel@nongnu.org; Tue, 05 Mar 2013 22:45:24 -0500 Received: from ozlabs.org ([2402:b800:7003:1:1::1]:57170) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UD5Hg-0007o0-T2; Tue, 05 Mar 2013 22:44:53 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 214062C0392; Wed, 6 Mar 2013 14:44:43 +1100 (EST) From: David Gibson To: agraf@suse.de Date: Wed, 6 Mar 2013 14:44:14 +1100 Message-Id: <1362541473-4365-27-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1362541473-4365-1-git-send-email-david@gibson.dropbear.id.au> References: <1362541473-4365-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2402:b800:7003:1:1::1 Cc: David Gibson , qemu-ppc@nongnu.org, afaerber@suse.de, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 26/45] mmu-hash*: Separate PTEG searching from permissions checking X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org find_pte{32,64{() do several things. First they search through a PTEG ooking for a PTE matching our virtual address. Then they do permissions checking and other processing on that PTE. This patch separates the search by VA out from the rest. The search is combined with the pte{32,64}_match() functions into new ppc_has{32,64}_pteg_search() functions. Signed-off-by: David Gibson --- target-ppc/mmu-hash32.c | 69 ++++++++++++++++++++++++----------------------- target-ppc/mmu-hash32.h | 4 +++ target-ppc/mmu-hash64.c | 67 ++++++++++++++++++++++----------------------- target-ppc/mmu-hash64.h | 4 +++ 4 files changed, 77 insertions(+), 67 deletions(-) diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 3be1002..7c13a49 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -297,14 +297,6 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, } } -static bool pte32_match(target_ulong pte0, target_ulong pte1, - bool secondary, target_ulong ptem) -{ - return (pte0 & HPTE32_V_VALID) - && (secondary == !!(pte0 & HPTE32_V_SECONDARY)) - && HPTE32_V_COMPARE(pte0, ptem); -} - static int pte_check_hash32(struct mmu_ctx_hash32 *ctx, target_ulong pte0, target_ulong pte1, int rwx) { @@ -328,8 +320,8 @@ static int pte_check_hash32(struct mmu_ctx_hash32 *ctx, target_ulong pte0, return ret; } -static int ppc_hash32_pte_update_flags(struct mmu_ctx_hash32 *ctx, target_ulong *pte1p, - int ret, int rwx) +static int ppc_hash32_pte_update_flags(struct mmu_ctx_hash32 *ctx, + uint32_t *pte1p, int ret, int rwx) { int store = 0; @@ -358,40 +350,49 @@ hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash) return (hash * HASH_PTEG_SIZE_32) & env->htab_mask; } -/* PTE table lookup */ +static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off, + bool secondary, target_ulong ptem, + ppc_hash_pte32_t *pte) +{ + hwaddr pte_offset = pteg_off; + target_ulong pte0, pte1; + int i; + + for (i = 0; i < HPTES_PER_GROUP; i++) { + pte0 = ppc_hash32_load_hpte0(env, pte_offset); + pte1 = ppc_hash32_load_hpte1(env, pte_offset); + + if ((pte0 & HPTE32_V_VALID) + && (secondary == !!(pte0 & HPTE32_V_SECONDARY)) + && HPTE32_V_COMPARE(pte0, ptem)) { + pte->pte0 = pte0; + pte->pte1 = pte1; + return pte_offset; + } + + pte_offset += HASH_PTE_SIZE_32; + } + + return -1; +} + static int find_pte32(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, target_ulong eaddr, int h, int rwx, int target_page_bits) { - hwaddr pteg_off; - target_ulong pte0, pte1; - int i, good = -1; + hwaddr pteg_off, pte_offset; + ppc_hash_pte32_t pte; int ret; ret = -1; /* No entry found */ pteg_off = get_pteg_offset32(env, ctx->hash[h]); - for (i = 0; i < HPTES_PER_GROUP; i++) { - pte0 = ppc_hash32_load_hpte0(env, pteg_off + i*HASH_PTE_SIZE_32); - pte1 = ppc_hash32_load_hpte1(env, pteg_off + i*HASH_PTE_SIZE_32); - - LOG_MMU("Load pte from %08" HWADDR_PRIx " => " TARGET_FMT_lx " " - TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", - pteg_off + (i * 8), pte0, pte1, (int)(pte0 >> 31), h, - (int)((pte0 >> 6) & 1), ctx->ptem); - - if (pte32_match(pte0, pte1, h, ctx->ptem)) { - good = i; - break; - } - } - if (good != -1) { - ret = pte_check_hash32(ctx, pte0, pte1, rwx); + pte_offset = ppc_hash32_pteg_search(env, pteg_off, h, ctx->ptem, &pte); + if (pte_offset != -1) { + ret = pte_check_hash32(ctx, pte.pte0, pte.pte1, rwx); LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n", ctx->raddr, ctx->prot, ret); /* Update page flags */ - pte1 = ctx->raddr; - if (ppc_hash32_pte_update_flags(ctx, &pte1, ret, rwx) == 1) { - ppc_hash32_store_hpte1(env, pteg_off + good * HASH_PTE_SIZE_32, - pte1); + if (ppc_hash32_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) { + ppc_hash32_store_hpte1(env, pte_offset, pte.pte1); } } diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h index 89488c5..d6e9330 100644 --- a/target-ppc/mmu-hash32.h +++ b/target-ppc/mmu-hash32.h @@ -95,4 +95,8 @@ static inline void ppc_hash32_store_hpte1(CPUPPCState *env, stl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1); } +typedef struct { + uint32_t pte0, pte1; +} ppc_hash_pte32_t; + #endif /* __MMU_HASH32_H__ */ diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 8664116..66b2d24 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -299,14 +299,6 @@ static int ppc_hash64_check_prot(int prot, int rwx) return ret; } -static bool pte64_match(target_ulong pte0, target_ulong pte1, - bool secondary, target_ulong ptem) -{ - return (pte0 & HPTE64_V_VALID) - && (secondary == !!(pte0 & HPTE64_V_SECONDARY)) - && HPTE64_V_COMPARE(pte0, ptem); -} - static int pte64_check(struct mmu_ctx_hash64 *ctx, target_ulong pte0, target_ulong pte1, int rwx) { @@ -334,8 +326,7 @@ static int pte64_check(struct mmu_ctx_hash64 *ctx, target_ulong pte0, } static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx, - target_ulong *pte1p, - int ret, int rw) + uint64_t *pte1p, int ret, int rw) { int store = 0; @@ -359,39 +350,49 @@ static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx, return store; } -/* PTE table lookup */ +static hwaddr ppc_hash64_pteg_search(CPUPPCState *env, hwaddr pteg_off, + bool secondary, target_ulong ptem, + ppc_hash_pte64_t *pte) +{ + hwaddr pte_offset = pteg_off; + target_ulong pte0, pte1; + int i; + + for (i = 0; i < HPTES_PER_GROUP; i++) { + pte0 = ppc_hash64_load_hpte0(env, pte_offset); + pte1 = ppc_hash64_load_hpte1(env, pte_offset); + + if ((pte0 & HPTE64_V_VALID) + && (secondary == !!(pte0 & HPTE64_V_SECONDARY)) + && HPTE64_V_COMPARE(pte0, ptem)) { + pte->pte0 = pte0; + pte->pte1 = pte1; + return pte_offset; + } + + pte_offset += HASH_PTE_SIZE_64; + } + + return -1; +} + static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, target_ulong eaddr, int h, int rwx, int target_page_bits) { - hwaddr pteg_off; - target_ulong pte0, pte1; - int i, good = -1; + hwaddr pteg_off, pte_offset; + ppc_hash_pte64_t pte; int ret; ret = -1; /* No entry found */ pteg_off = (ctx->hash[h] * HASH_PTEG_SIZE_64) & env->htab_mask; - for (i = 0; i < HPTES_PER_GROUP; i++) { - pte0 = ppc_hash64_load_hpte0(env, pteg_off + i*HASH_PTE_SIZE_64); - pte1 = ppc_hash64_load_hpte1(env, pteg_off + i*HASH_PTE_SIZE_64); - - LOG_MMU("Load pte from %016" HWADDR_PRIx " => " TARGET_FMT_lx " " - TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", - pteg_off + (i * 16), pte0, pte1, !!(pte0 & HPTE64_V_VALID), - h, !!(pte0 & HPTE64_V_SECONDARY), ctx->ptem); - - if (pte64_match(pte0, pte1, h, ctx->ptem)) { - good = i; - break; - } - } - if (good != -1) { - ret = pte64_check(ctx, pte0, pte1, rwx); + pte_offset = ppc_hash64_pteg_search(env, pteg_off, h, ctx->ptem, &pte); + if (pte_offset != -1) { + ret = pte64_check(ctx, pte.pte0, pte.pte1, rwx); LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n", ctx->raddr, ctx->prot, ret); /* Update page flags */ - pte1 = ctx->raddr; - if (ppc_hash64_pte_update_flags(ctx, &pte1, ret, rwx) == 1) { - ppc_hash64_store_hpte1(env, pteg_off + good * HASH_PTE_SIZE_64, pte1); + if (ppc_hash64_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) { + ppc_hash64_store_hpte1(env, pte_offset, pte.pte1); } } diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h index 302c3d5..efbc7e1 100644 --- a/target-ppc/mmu-hash64.h +++ b/target-ppc/mmu-hash64.h @@ -111,4 +111,8 @@ static inline void ppc_hash64_store_hpte1(CPUPPCState *env, } } +typedef struct { + uint64_t pte0, pte1; +} ppc_hash_pte64_t; + #endif /* !defined (__MMU_HASH64_H__) */