From patchwork Wed Mar 6 03:44:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 225278 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 57FED2C0374 for ; Wed, 6 Mar 2013 14:56:55 +1100 (EST) Received: from localhost ([::1]:50399 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UD5Qb-0002rr-7N for incoming@patchwork.ozlabs.org; Tue, 05 Mar 2013 22:54:05 -0500 Received: from eggs.gnu.org ([208.118.235.92]:51583) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UD5ID-0004EB-N3 for qemu-devel@nongnu.org; Tue, 05 Mar 2013 22:46:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UD5Hi-0007tj-0p for qemu-devel@nongnu.org; Tue, 05 Mar 2013 22:45:25 -0500 Received: from ozlabs.org ([203.10.76.45]:37147) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UD5Hh-0007nr-CZ; Tue, 05 Mar 2013 22:44:53 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 6765D2C0396; Wed, 6 Mar 2013 14:44:43 +1100 (EST) From: David Gibson To: agraf@suse.de Date: Wed, 6 Mar 2013 14:44:18 +1100 Message-Id: <1362541473-4365-31-git-send-email-david@gibson.dropbear.id.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1362541473-4365-1-git-send-email-david@gibson.dropbear.id.au> References: <1362541473-4365-1-git-send-email-david@gibson.dropbear.id.au> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 203.10.76.45 Cc: David Gibson , qemu-ppc@nongnu.org, afaerber@suse.de, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH 30/45] mmu-hash*: Fold pte_check*() logic into caller X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org With previous cleanups made, the 32-bit and 64-bit pte_check*() functions are pretty trivial and only have one call site. This patch therefore clarifies the overall code flow by folding those functions into their call site. Signed-off-by: David Gibson --- target-ppc/mmu-hash32.c | 48 +++++++++++++++++++++------------------------ target-ppc/mmu-hash64.c | 50 ++++++++++++++++++++++------------------------- 2 files changed, 45 insertions(+), 53 deletions(-) diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index 8b403fe..53e86de 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -295,31 +295,8 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr, } } -static int pte_check_hash32(struct mmu_ctx_hash32 *ctx, target_ulong pte0, - target_ulong pte1, int rwx) -{ - int access, ret, pp; - - pp = pte1 & HPTE32_R_PP; - /* Compute access rights */ - access = ppc_hash32_pp_check(ctx->key, pp, ctx->nx); - /* Keep the matching PTE informations */ - ctx->raddr = pte1; - ctx->prot = access; - ret = ppc_hash32_check_prot(ctx->prot, rwx); - if (ret == 0) { - /* Access granted */ - LOG_MMU("PTE access granted !\n"); - } else { - /* Access right violation */ - LOG_MMU("PTE access rejected\n"); - } - - return ret; -} - -static int ppc_hash32_pte_update_flags(struct mmu_ctx_hash32 *ctx, - uint32_t *pte1p, int ret, int rwx) +static int ppc_hash32_pte_update_flags(struct mmu_ctx_hash32 *ctx, uint32_t *pte1p, + int ret, int rwx) { int store = 0; @@ -420,6 +397,8 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, hwaddr pte_offset; ppc_hash_pte32_t pte; + assert((rwx == 0) || (rwx == 1) || (rwx == 2)); + /* 1. Handle real mode accesses */ if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { /* Translation is off */ @@ -461,7 +440,24 @@ static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx, /* 7. Check access permissions */ ctx->key = (((sr & SR32_KP) && (msr_pr != 0)) || ((sr & SR32_KS) && (msr_pr == 0))) ? 1 : 0; - ret = pte_check_hash32(ctx, pte.pte0, pte.pte1, rwx); + + int access, pp; + + pp = pte.pte1 & HPTE32_R_PP; + /* Compute access rights */ + access = ppc_hash32_pp_check(ctx->key, pp, ctx->nx); + /* Keep the matching PTE informations */ + ctx->raddr = pte.pte1; + ctx->prot = access; + ret = ppc_hash32_check_prot(ctx->prot, rwx); + if (ret == 0) { + /* Access granted */ + LOG_MMU("PTE access granted !\n"); + } else { + /* Access right violation */ + LOG_MMU("PTE access rejected\n"); + } + /* Update page flags */ if (ppc_hash32_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) { ppc_hash32_store_hpte1(env, pte_offset, pte.pte1); diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 10372f0..2e109f4 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -297,32 +297,6 @@ static int ppc_hash64_check_prot(int prot, int rwx) return ret; } -static int pte64_check(struct mmu_ctx_hash64 *ctx, target_ulong pte0, - target_ulong pte1, int rwx) -{ - int access, ret, pp; - bool nx; - - pp = (pte1 & HPTE64_R_PP) | ((pte1 & HPTE64_R_PP0) >> 61); - /* No execute if either noexec or guarded bits set */ - nx = (pte1 & HPTE64_R_N) || (pte1 & HPTE64_R_G); - /* Compute access rights */ - access = ppc_hash64_pp_check(ctx->key, pp, nx); - /* Keep the matching PTE informations */ - ctx->raddr = pte1; - ctx->prot = access; - ret = ppc_hash64_check_prot(ctx->prot, rwx); - if (ret == 0) { - /* Access granted */ - LOG_MMU("PTE access granted !\n"); - } else { - /* Access right violation */ - LOG_MMU("PTE access rejected\n"); - } - - return ret; -} - static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx, uint64_t *pte1p, int ret, int rw) { @@ -439,6 +413,8 @@ static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, ppc_hash_pte64_t pte; int target_page_bits; + assert((rwx == 0) || (rwx == 1) || (rwx == 2)); + /* 1. Handle real mode accesses */ if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { /* Translation is off */ @@ -471,7 +447,27 @@ static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, ctx->key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP) : (slb->vsid & SLB_VSID_KS)); - ret = pte64_check(ctx, pte.pte0, pte.pte1, rwx); + + int access, pp; + bool nx; + + pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61); + /* No execute if either noexec or guarded bits set */ + nx = (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G); + /* Compute access rights */ + access = ppc_hash64_pp_check(ctx->key, pp, nx); + /* Keep the matching PTE informations */ + ctx->raddr = pte.pte1; + ctx->prot = access; + ret = ppc_hash64_check_prot(ctx->prot, rwx); + if (ret == 0) { + /* Access granted */ + LOG_MMU("PTE access granted !\n"); + } else { + /* Access right violation */ + LOG_MMU("PTE access rejected\n"); + } + /* Update page flags */ if (ppc_hash64_pte_update_flags(ctx, &pte.pte1, ret, rwx) == 1) { ppc_hash64_store_hpte1(env, pte_offset, pte.pte1);