Patchwork [3/8] powerpc/fsl-booke: Support detection of page sizes on

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Submitter Kumar Gala
Date March 5, 2013, 11:15 p.m.
Message ID <1362525360-23136-3-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/225196/
State Accepted, archived
Commit 1b29187315993cc34e9c73d4d8a0887a10cd8998
Delegated to: Kumar Gala
Headers show

Comments

Kumar Gala - March 5, 2013, 11:15 p.m.
The e6500 core used on T4240 and B4860 SoCs from FSL implements MMUv2 of
the Power Book-E Architecture.  However there are some minor differences
between it and other Book-E implementations.

Add support to parse SPRN_TLB1PS for the variable page sizes supported.
In the future this should be expanded for more page sizes supported on
e6500 as well as other MMU features.

This patch is based on code from Scott Wood.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/mm/tlb_nohash.c |   18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)
Kumar Gala - March 12, 2013, 9:15 p.m.
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:

> The e6500 core used on T4240 and B4860 SoCs from FSL implements MMUv2 of
> the Power Book-E Architecture.  However there are some minor differences
> between it and other Book-E implementations.
> 
> Add support to parse SPRN_TLB1PS for the variable page sizes supported.
> In the future this should be expanded for more page sizes supported on
> e6500 as well as other MMU features.
> 
> This patch is based on code from Scott Wood.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/mm/tlb_nohash.c |   18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)

applied to next

- k

Patch

diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index df32a83..6888cad 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -414,9 +414,9 @@  static void setup_page_sizes(void)
 
 #ifdef CONFIG_PPC_FSL_BOOK3E
 	unsigned int mmucfg = mfspr(SPRN_MMUCFG);
+	int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
 
-	if (((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) &&
-		(mmu_has_feature(MMU_FTR_TYPE_FSL_E))) {
+	if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
 		unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
 		unsigned int min_pg, max_pg;
 
@@ -442,6 +442,20 @@  static void setup_page_sizes(void)
 
 		goto no_indirect;
 	}
+
+	if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
+		u32 tlb1ps = mfspr(SPRN_TLB1PS);
+
+		for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
+			struct mmu_psize_def *def = &mmu_psize_defs[psize];
+
+			if (tlb1ps & (1U << (def->shift - 10))) {
+				def->flags |= MMU_PAGE_SIZE_DIRECT;
+			}
+		}
+
+		goto no_indirect;
+	}
 #endif
 
 	tlb0cfg = mfspr(SPRN_TLB0CFG);