Patchwork [v2,2/3] pc: port 92 reset requires a low->high transition

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Submitter Paolo Bonzini
Date March 5, 2013, 7 p.m.
Message ID <1362510056-3316-3-git-send-email-pbonzini@redhat.com>
Download mbox | patch
Permalink /patch/225165/
State New
Headers show

Comments

Paolo Bonzini - March 5, 2013, 7 p.m.
The PIIX datasheet says that "before another INIT pulse can be
generated via [port 92h], [bit 0] must be written back to a
zero.

This bug is masked right now because a full reset will clear the
value of port 92h.  But once we implement soft reset correctly,
the next attempt to enable the A20 line by setting bit 1 (and
leaving the others untouched) will cause another reset.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 hw/pc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Patch

diff --git a/hw/pc.c b/hw/pc.c
index 37f6b52..3e1cf2e 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -437,11 +437,12 @@  static void port92_write(void *opaque, hwaddr addr, uint64_t val,
                          unsigned size)
 {
     Port92State *s = opaque;
+    int oldval = s->outport;
 
     DPRINTF("port92: write 0x%02x\n", val);
     s->outport = val;
     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
-    if (val & 1) {
+    if ((val & 1) && !(oldval & 1)) {
         qemu_system_reset_request();
     }
 }