From patchwork Tue Mar 5 16:29:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 225081 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F27C52C007C for ; Wed, 6 Mar 2013 03:31:12 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5C1844A1A5; Tue, 5 Mar 2013 17:31:08 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tTc28hOaMSSf; Tue, 5 Mar 2013 17:31:08 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9736A4A04E; Tue, 5 Mar 2013 17:30:46 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7BF654A178 for ; Tue, 5 Mar 2013 17:30:33 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BsaI1J64mYJG for ; Tue, 5 Mar 2013 17:30:27 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f53.google.com (mail-pb0-f53.google.com [209.85.160.53]) by theia.denx.de (Postfix) with ESMTPS id 1A5C74A176 for ; Tue, 5 Mar 2013 17:30:25 +0100 (CET) Received: by mail-pb0-f53.google.com with SMTP id un1so4621073pbc.40 for ; Tue, 05 Mar 2013 08:30:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-nvconfidentiality; bh=AILyhUG+qOduWudEOzT2+wn++ZQxtAdZrjIhqbHzIjo=; b=bSAp3yy3uaFi28IzqsWei4/qwniqAhM1wURRwZpUZyJxqR71/s5zPGVagJ/kBABJDC EEVxEmlsvwwRwzgbBThL212QZyZH5HegDCeTuJ9MiK0Cu0s5y7OOSg7FLydEaLiena/y pmgeYD0u6zqEhzoPHrUs//DSBYb+9xXcMbOoUoUAuk+wS5Diyrzb5YmJ+5+ehq4Ax3ZD Pq0hqYiMMWWldDgvGSTxsH2zkpbcMMIl5rKSn06baihRnOWQaGbuYQArRjuX6pLWhzE7 vYVELN+iV7ImGlOH95QaLcQjPgDcaa5FUxOWBAail5T8m0fNaq7VQcgZQZcqZ+qys24b wZNg== X-Received: by 10.68.25.201 with SMTP id e9mr37926065pbg.145.1362501023749; Tue, 05 Mar 2013 08:30:23 -0800 (PST) Received: from localhost.localdomain (ip68-230-103-25.ph.ph.cox.net. [68.230.103.25]) by mx.google.com with ESMTPS id qp13sm27311372pbb.3.2013.03.05.08.30.21 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 05 Mar 2013 08:30:22 -0800 (PST) From: Tom Warren To: u-boot@lists.denx.de Date: Tue, 5 Mar 2013 09:29:41 -0700 Message-Id: <1362500985-13196-3-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1362500985-13196-1-git-send-email-twarren@nvidia.com> References: <1362500985-13196-1-git-send-email-twarren@nvidia.com> X-NVConfidentiality: public Cc: swarren@nvidia.com, afleming@freescale.com, Tom Warren , twarren.nvidia@gmail.com Subject: [U-Boot] [PATCH v2 2/6] Tegra: MMC: Added/update SDMMC registers/base addresses for T20/T30 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Removed SDMMC base addresses from tegra.h since they're no longer used. Added pad control settings for T30 from the TRM, and added additional vendor-specific SD/MMC registers and bus power defines. Signed-off-by: Tom Warren --- v2: - change pad_init_mmc prototype - remove all TEGRA_SDMMCx_BASE defines arch/arm/include/asm/arch-tegra/tegra_mmc.h | 35 +++++++++++++++++++---- arch/arm/include/asm/arch-tegra30/gp_padctrl.h | 6 ++++ 2 files changed, 35 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index bd18f5f..2a3f830 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -22,10 +22,7 @@ #ifndef __TEGRA_MMC_H_ #define __TEGRA_MMC_H_ -#define TEGRA_SDMMC1_BASE 0xC8000000 -#define TEGRA_SDMMC2_BASE 0xC8000200 -#define TEGRA_SDMMC3_BASE 0xC8000400 -#define TEGRA_SDMMC4_BASE 0xC8000600 +#include #define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */ @@ -64,12 +61,30 @@ struct tegra_mmc { unsigned char admaerr; /* offset 54h */ unsigned char res4[3]; /* RESERVED, offset 55h-57h */ unsigned long admaaddr; /* offset 58h-5Fh */ - unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */ + unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */ unsigned short slotintstatus; /* offset FCh */ unsigned short hcver; /* HOST Version */ - unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */ + unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ + unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */ + unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */ + unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */ + unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */ + unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */ + unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */ + unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */ + unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */ + unsigned int res6[47]; /* 0x124 ~ 0x1DC */ + unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */ + unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */ + unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */ + unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */ }; +#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0) +#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1) +#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1) +#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1) + #define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) @@ -119,6 +134,12 @@ struct tegra_mmc { #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) +/* SDMMC1/3 settings from section 24.6 of T30 TRM */ +#define MEMCOMP_PADCTRL_VREF 7 +#define AUTO_CAL_ENABLED (1 << 29) +#define AUTO_CAL_PD_OFFSET (0x70 << 8) +#define AUTO_CAL_PU_OFFSET (0x62 << 0) + struct mmc_host { struct tegra_mmc *reg; int id; /* device id/number, 0-3 */ @@ -132,5 +153,7 @@ struct mmc_host { unsigned int clock; /* Current clock (MHz) */ }; +void pad_init_mmc(struct mmc_host *host); + #endif /* __ASSEMBLY__ */ #endif /* __TEGRA_MMC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h index 9b383d0..48b9a3b 100644 --- a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h @@ -56,4 +56,10 @@ struct apb_misc_gp_ctlr { u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ }; +/* SDMMC1/3 settings from section 24.6 of T30 TRM */ +#define GP_SDIOCFG_DRVUP_SLWF (1 << 30) +#define GP_SDIOCFG_DRVDN_SLWR (1 << 28) +#define GP_SDIOCFG_DRVUP (0x2E << 20) +#define GP_SDIOCFG_DRVDN (0x2A << 12) + #endif /* _TEGRA30_GP_PADCTRL_H_ */