From patchwork Tue Mar 5 16:29:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Warren X-Patchwork-Id: 225080 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 385B62C007C for ; Wed, 6 Mar 2013 03:31:00 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E34524A18B; Tue, 5 Mar 2013 17:30:57 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5L8WaYDMWimF; Tue, 5 Mar 2013 17:30:57 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9B3AA4A19A; Tue, 5 Mar 2013 17:30:40 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7B3604A175 for ; Tue, 5 Mar 2013 17:30:33 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xc6fxuv4iGD3 for ; Tue, 5 Mar 2013 17:30:29 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f44.google.com (mail-pb0-f44.google.com [209.85.160.44]) by theia.denx.de (Postfix) with ESMTPS id 552334A174 for ; Tue, 5 Mar 2013 17:30:28 +0100 (CET) Received: by mail-pb0-f44.google.com with SMTP id wz12so4666191pbc.17 for ; Tue, 05 Mar 2013 08:30:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-nvconfidentiality; bh=GOvZqxkck6ztHe7Sg4hCLUwgfJwb4GPHCkE5XD2rLE0=; b=duBtqJO4PW4S5IM9BdWhhImBzDLEzf2PqwkJ0FUERoT7POm3pS+EOi5LSQiRs7Cs8H HMKWdvRCcmi8cvoQLm8K3TdSGxEnTF1n48hsSacNsTEwQv2ZBWDyfNRfTGXRiJZBmLix HNaNleOuc3dAsoLbQvFpGMygCatriuBVz+aLJ2BMQ7fC1i+Qtmr8H7L9/u0rJkEmJR2Z 3F/909qEQ3jhkO5o0juygrl8FeHyjGuhSqJUG/v86uk+sqQbcR/UkCK56nGpwZTO8MJE T0nZJkHw9loiQbVZlLOEWp4CSZuTM8eeafVT9biK01HSA0ULUPvUcXL1C3f6Bvo6PXi7 h+Cw== X-Received: by 10.68.224.225 with SMTP id rf1mr38750521pbc.9.1362501026584; Tue, 05 Mar 2013 08:30:26 -0800 (PST) Received: from localhost.localdomain (ip68-230-103-25.ph.ph.cox.net. [68.230.103.25]) by mx.google.com with ESMTPS id qp13sm27311372pbb.3.2013.03.05.08.30.23 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 05 Mar 2013 08:30:25 -0800 (PST) From: Tom Warren To: u-boot@lists.denx.de Date: Tue, 5 Mar 2013 09:29:42 -0700 Message-Id: <1362500985-13196-4-git-send-email-twarren@nvidia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1362500985-13196-1-git-send-email-twarren@nvidia.com> References: <1362500985-13196-1-git-send-email-twarren@nvidia.com> X-NVConfidentiality: public Cc: swarren@nvidia.com, afleming@freescale.com, Tom Warren , twarren.nvidia@gmail.com Subject: [U-Boot] [PATCH v2 3/6] Tegra30: MMC: Add SD bus power-rail and SDMMC pad init routines X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de T30 requires specific SDMMC pad programming, and bus power-rail bringup. Signed-off-by: Tom Warren --- v2: - rewrite pad_init_mmc to use mmc_id instead of SDMMC base address - add PMU-specific comments to board_sdmmc_voltage_init sequence board/nvidia/cardhu/cardhu.c | 51 ++++++++++++++++++++++++++++++++++++++ board/nvidia/common/board.c | 55 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 105 insertions(+), 1 deletions(-) diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index df4cb6b..1889998 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -24,6 +24,10 @@ #include #include #include "pinmux-config-cardhu.h" +#include + +#define PMU_I2C_ADDRESS 0x2D +#define MAX_I2C_RETRY 3 /* * Routine: pinmux_init @@ -37,3 +41,50 @@ void pinmux_init(void) pinmux_config_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); } + +#if defined(CONFIG_TEGRA_MMC) +/* + * Do I2C/PMU writes to bring up SD card bus power + * + */ +void board_sdmmc_voltage_init(void) +{ + uchar reg, data_buffer[1]; + int i; + + i2c_set_bus_num(0); /* PMU is on bus 0 */ + + /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */ + data_buffer[0] = 0x65; + reg = 0x32; + + for (i = 0; i < MAX_I2C_RETRY; ++i) { + if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) + udelay(100); + } + + /* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */ + data_buffer[0] = 0x09; + reg = 0x67; + + for (i = 0; i < MAX_I2C_RETRY; ++i) { + if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1)) + udelay(100); + } +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* + * NOTE: We don't do mmc-specific pin muxes here. + * They were done globally in pinmux_init(). + */ + + /* Bring up the SDIO1 power rail */ + board_sdmmc_voltage_init(); +} +#endif /* MMC */ diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index babbe08..8c9040d 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -49,6 +49,8 @@ #include #endif #ifdef CONFIG_TEGRA_MMC +#include +#include #include #endif #include @@ -245,4 +247,55 @@ int board_mmc_init(bd_t *bd) return 0; } -#endif + +void pad_init_mmc(struct mmc_host *host) +{ +#if defined(CONFIG_TEGRA30) + struct apb_misc_gp_ctlr *const gpc = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; + enum periph_id id; + u32 val, padcfg, padmask; + + id = host->mmc_id; + + debug("%s: sdmmc address = %08x, id = %d\n", __func__, + (unsigned int)host->reg, id); + + /* Set the pad drive strength for SDMMC1 or 3 only */ + if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { + debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", + __func__); + return; + } + + /* Set pads as per T30 TRM, section 24.6.1.2 */ + padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \ + GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN); + padmask = 0x00000FFF; + + if (id == PERIPH_ID_SDMMC1) { + val = readl(&gpc->sdio1cfg); + val &= padmask; + val |= padcfg; + writel(val, &gpc->sdio1cfg); + debug(" wrote 0x%08X to %p\n", val, &gpc->sdio1cfg); + } else { + val = readl(&gpc->sdio3cfg); + val &= padmask; + val |= padcfg; + writel(val, &gpc->sdio3cfg); + debug(" wrote 0x%08X to %p\n", val, &gpc->sdio3cfg); + } + + val = readl(&host->reg->sdmemcmppadctl); + val &= 0xFFFFFFF0; + val |= MEMCOMP_PADCTRL_VREF; + writel(val, &host->reg->sdmemcmppadctl); + + val = readl(&host->reg->autocalcfg); + val &= 0xFFFF0000; + val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; + writel(val, &host->reg->autocalcfg); +#endif /* T30 */ +} +#endif /* MMC */