From patchwork Tue Mar 5 15:04:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 225057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BD1BF2C0329 for ; Wed, 6 Mar 2013 02:34:21 +1100 (EST) Received: from localhost ([::1]:45250 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCtsh-0004Mb-PD for incoming@patchwork.ozlabs.org; Tue, 05 Mar 2013 10:34:19 -0500 Received: from eggs.gnu.org ([208.118.235.92]:54736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCtsO-0004MM-Cr for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:34:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCtsN-00086k-6L for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:34:00 -0500 Received: from mail-wg0-f48.google.com ([74.125.82.48]:42980) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCtQS-0007te-4Y for qemu-devel@nongnu.org; Tue, 05 Mar 2013 10:05:08 -0500 Received: by mail-wg0-f48.google.com with SMTP id 16so5714959wgi.15 for ; Tue, 05 Mar 2013 07:05:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=vJLlQe8nlSvKvos7EoFOhdoS84/+MvYHNQ5oZjvVTw4=; b=Bzp50rzyg6mj/r/qanI/CZcodc2UxyQpuZbECfuQOeR+6PWpHPXHOGNJ4irDe0+ZoE 6Fte6ePgt6g7tSed8LKhvzFoupidSKwjz/vkwOTw3DEsxXeRuLkYECgOVZ+Vfh1FucDy 7Dw5gIVGbhF1DUqlSyng/6YUChr91B4/WJfIUAZYiMHBdadjPD/RR4aOt3uR2WS03T9l ENgQPz2VEKXUUWEy82bg/BVA4D8E0BSAh5R9kAEbXh3UVytZ3eJ6N/XwY6hzbFRkyWr4 cB+LvpZXgvFPmSn4yqIWEX5ZTq69DMlscHhLwC6MLYykgjZ4ghU/uF/6LJhcoAKP8JVt 7qFQ== X-Received: by 10.194.10.202 with SMTP id k10mr39778797wjb.53.1362495907479; Tue, 05 Mar 2013 07:05:07 -0800 (PST) Received: from playground.lan (93-34-176-20.ip50.fastwebnet.it. [93.34.176.20]) by mx.google.com with ESMTPS id dm9sm11529733wib.3.2013.03.05.07.05.06 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 05 Mar 2013 07:05:06 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Date: Tue, 5 Mar 2013 16:04:57 +0100 Message-Id: <1362495898-15352-3-git-send-email-pbonzini@redhat.com> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1362495898-15352-1-git-send-email-pbonzini@redhat.com> References: <1362495898-15352-1-git-send-email-pbonzini@redhat.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 74.125.82.48 Cc: lersek@redhat.com, aliguori@us.ibm.com, dwmw2@infradead.org Subject: [Qemu-devel] [PATCH 2/3] pc: port 92 reset requires a low->high transition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The PIIX datasheet says that "before another INIT pulse can be generated via [port 92h], [bit 0] must be written back to a zero. This bug is masked right now because a full reset will clear the value of port 92h. But once we implement soft reset correctly, the next attempt to enable the A20 line by setting bit 1 (and leaving the others untouched) will cause another reset. Signed-off-by: Paolo Bonzini Reviewed-by: Anthony Liguori Reviewed-by: Laszlo Ersek --- hw/pc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/pc.c b/hw/pc.c index 07caba7..523db1f 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -435,11 +435,12 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { Port92State *s = opaque; + int oldval = s->outport; DPRINTF("port92: write 0x%02x\n", val); s->outport = val; qemu_set_irq(*s->a20_out, (val >> 1) & 1); - if (val & 1) { + if ((val & 1) && !(oldval & 1)) { qemu_system_reset_request(); } }