Patchwork [2/3] pc: port 92 reset requires a low->high transition

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Submitter Paolo Bonzini
Date March 5, 2013, 3:04 p.m.
Message ID <1362495898-15352-3-git-send-email-pbonzini@redhat.com>
Download mbox | patch
Permalink /patch/225057/
State New
Headers show

Comments

Paolo Bonzini - March 5, 2013, 3:04 p.m.
The PIIX datasheet says that "before another INIT pulse can be
generated via [port 92h], [bit 0] must be written back to a
zero.

This bug is masked right now because a full reset will clear the
value of port 92h.  But once we implement soft reset correctly,
the next attempt to enable the A20 line by setting bit 1 (and
leaving the others untouched) will cause another reset.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 hw/pc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
Anthony Liguori - March 5, 2013, 5:20 p.m.
Paolo Bonzini <pbonzini@redhat.com> writes:

> The PIIX datasheet says that "before another INIT pulse can be
> generated via [port 92h], [bit 0] must be written back to a
> zero.
>
> This bug is masked right now because a full reset will clear the
> value of port 92h.  But once we implement soft reset correctly,
> the next attempt to enable the A20 line by setting bit 1 (and
> leaving the others untouched) will cause another reset.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>

Regards,

Anthony Liguori

> ---
>  hw/pc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index 07caba7..523db1f 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -435,11 +435,12 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val,
>                           unsigned size)
>  {
>      Port92State *s = opaque;
> +    int oldval = s->outport;
>  
>      DPRINTF("port92: write 0x%02x\n", val);
>      s->outport = val;
>      qemu_set_irq(*s->a20_out, (val >> 1) & 1);
> -    if (val & 1) {
> +    if ((val & 1) && !(oldval & 1)) {
>          qemu_system_reset_request();
>      }
>  }
> -- 
> 1.8.1.4
Laszlo Ersek - March 5, 2013, 6:05 p.m.
On 03/05/13 16:04, Paolo Bonzini wrote:
> The PIIX datasheet says that "before another INIT pulse can be
> generated via [port 92h], [bit 0] must be written back to a
> zero.
> 
> This bug is masked right now because a full reset will clear the
> value of port 92h.  But once we implement soft reset correctly,
> the next attempt to enable the A20 line by setting bit 1 (and
> leaving the others untouched) will cause another reset.
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  hw/pc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/pc.c b/hw/pc.c
> index 07caba7..523db1f 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -435,11 +435,12 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val,
>                           unsigned size)
>  {
>      Port92State *s = opaque;
> +    int oldval = s->outport;
>  
>      DPRINTF("port92: write 0x%02x\n", val);
>      s->outport = val;
>      qemu_set_irq(*s->a20_out, (val >> 1) & 1);
> -    if (val & 1) {
> +    if ((val & 1) && !(oldval & 1)) {
>          qemu_system_reset_request();
>      }
>  }
> 

Reviewed-by: Laszlo Ersek <lersek@redhat.com>

Patch

diff --git a/hw/pc.c b/hw/pc.c
index 07caba7..523db1f 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -435,11 +435,12 @@  static void port92_write(void *opaque, hwaddr addr, uint64_t val,
                          unsigned size)
 {
     Port92State *s = opaque;
+    int oldval = s->outport;
 
     DPRINTF("port92: write 0x%02x\n", val);
     s->outport = val;
     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
-    if (val & 1) {
+    if ((val & 1) && !(oldval & 1)) {
         qemu_system_reset_request();
     }
 }