From patchwork Tue Mar 5 01:12:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 224910 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3DF652C033B for ; Tue, 5 Mar 2013 12:56:33 +1100 (EST) Received: from localhost ([::1]:42000 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCh7H-0003QS-GN for incoming@patchwork.ozlabs.org; Mon, 04 Mar 2013 20:56:31 -0500 Received: from eggs.gnu.org ([208.118.235.92]:34208) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCh6t-0003Il-FR for qemu-devel@nongnu.org; Mon, 04 Mar 2013 20:56:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCh6p-0001V9-UT for qemu-devel@nongnu.org; Mon, 04 Mar 2013 20:56:07 -0500 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:60962 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCh6p-0001Us-Lw for qemu-devel@nongnu.org; Mon, 04 Mar 2013 20:56:03 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1UCgQO-00019M-6w; Tue, 05 Mar 2013 01:12:12 +0000 From: Peter Maydell To: Aurelien Jarno , Blue Swirl Date: Tue, 5 Mar 2013 01:12:05 +0000 Message-Id: <1362445931-4383-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1362445931-4383-1-git-send-email-peter.maydell@linaro.org> References: <1362445931-4383-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: Anthony Liguori , qemu-devel@nongnu.org, Paul Brook Subject: [Qemu-devel] [PATCH 07/13] ARM KVM: save and load VFP registers from kernel X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add support for saving and restoring VFP register state from the kernel. This includes a check that the KVM-created CPU has full VFP support (as the TCG Cortex-A15 model always does), since for the moment ARM QEMU doesn't have any way to tweak optional features on created CPUs. Signed-off-by: Peter Maydell Reviewed-by: Paolo Bonzini --- target-arm/kvm.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 75 insertions(+), 3 deletions(-) diff --git a/target-arm/kvm.c b/target-arm/kvm.c index 499b427..9173d0a 100644 --- a/target-arm/kvm.c +++ b/target-arm/kvm.c @@ -43,10 +43,28 @@ unsigned long kvm_arch_vcpu_id(CPUState *cpu) int kvm_arch_init_vcpu(CPUState *cs) { struct kvm_vcpu_init init; + int ret; + uint64_t v; + struct kvm_one_reg r; init.target = KVM_ARM_TARGET_CORTEX_A15; memset(init.features, 0, sizeof(init.features)); - return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); + ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); + if (ret) { + return ret; + } + /* Query the kernel to make sure it supports 32 VFP + * registers: QEMU's "cortex-a15" CPU is always a + * VFP-D32 core. The simplest way to do this is just + * to attempt to read register d31. + */ + r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31; + r.addr = (uintptr_t)(&v); + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + if (ret == ENOENT) { + return EINVAL; + } + return ret; } typedef struct Reg { @@ -72,6 +90,13 @@ typedef struct Reg { offsetof(CPUARMState, QEMUFIELD) \ } +#define VFPSYSREG(R) \ + { \ + KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \ + KVM_REG_ARM_VFP_##R, \ + offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \ + } + static const Reg regs[] = { /* R0_usr .. R14_usr */ COREREG(usr_regs.uregs[0], regs[0]), @@ -119,6 +144,13 @@ static const Reg regs[] = { CP15REG(1, 0, 0, 0, cp15.c1_sys), /* SCTLR */ CP15REG(2, 0, 0, 2, cp15.c2_control), /* TTBCR */ CP15REG(3, 0, 0, 0, cp15.c3), /* DACR */ + /* VFP system registers */ + VFPSYSREG(FPSID), + VFPSYSREG(MVFR1), + VFPSYSREG(MVFR0), + VFPSYSREG(FPEXC), + VFPSYSREG(FPINST), + VFPSYSREG(FPINST2), }; int kvm_arch_put_registers(CPUState *cs, int level) @@ -128,7 +160,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) struct kvm_one_reg r; int mode, bn; int ret, i; - uint32_t cpsr; + uint32_t cpsr, fpscr; uint64_t ttbr; /* Make sure the banked regs are properly set */ @@ -179,6 +211,26 @@ int kvm_arch_put_registers(CPUState *cs, int level) (2 << KVM_REG_ARM_CRM_SHIFT) | (1 << KVM_REG_ARM_OPC1_SHIFT); r.addr = (uintptr_t)(&ttbr); ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); + if (ret) { + return ret; + } + + /* VFP registers */ + r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; + for (i = 0; i < 32; i++) { + r.addr = (uintptr_t)(&env->vfp.regs[i]); + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); + if (ret) { + return ret; + } + r.id++; + } + + r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | + KVM_REG_ARM_VFP_FPSCR; + fpscr = vfp_get_fpscr(env); + r.addr = (uintptr_t)&fpscr; + ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); return ret; } @@ -190,7 +242,7 @@ int kvm_arch_get_registers(CPUState *cs) struct kvm_one_reg r; int mode, bn; int ret, i; - uint32_t cpsr; + uint32_t cpsr, fpscr; uint64_t ttbr; for (i = 0; i < ARRAY_SIZE(regs); i++) { @@ -255,6 +307,26 @@ int kvm_arch_get_registers(CPUState *cs) env->cp15.c2_mask = ~(0xffffffffu >> env->cp15.c2_control); env->cp15.c2_base_mask = ~(0x3fffu >> env->cp15.c2_control); + /* VFP registers */ + r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; + for (i = 0; i < 32; i++) { + r.addr = (uintptr_t)(&env->vfp.regs[i]); + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + if (ret) { + return ret; + } + r.id++; + } + + r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | + KVM_REG_ARM_VFP_FPSCR; + r.addr = (uintptr_t)&fpscr; + ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + if (ret) { + return ret; + } + vfp_set_fpscr(env, fpscr); + return 0; }