| Submitter | Richard Henderson |
|---|---|
| Date | March 5, 2013, 12:33 a.m. |
| Message ID | <1362443590-28191-20-git-send-email-rth@twiddle.net> |
| Download | mbox | patch |
| Permalink | /patch/224875/ |
| State | New |
| Headers | show |
Comments
On Mon, Mar 04, 2013 at 04:33:02PM -0800, Richard Henderson wrote: > Since we have special code to handle and/or/xor with a constant, > apply the same to andc/orc/eqv with a constant. > > Signed-off-by: Richard Henderson <rth@twiddle.net> > --- > tcg/ppc64/tcg-target.c | 44 ++++++++++++++++++++++++++++++++++---------- > 1 file changed, 34 insertions(+), 10 deletions(-) > > diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c > index a1be15a..c1d974b 100644 > --- a/tcg/ppc64/tcg-target.c > +++ b/tcg/ppc64/tcg-target.c > @@ -1388,17 +1388,19 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, > break; > > case INDEX_op_and_i32: > + a0 = args[0], a1 = args[1], a2 = args[2]; > if (const_args[2]) { > - tcg_out_andi32(s, args[0], args[1], args[2]); > + tcg_out_andi32(s, a0, a1, a2); > } else { > - tcg_out32(s, AND | SAB(args[1], args[0], args[2])); > + tcg_out32(s, AND | SAB(a1, a0, a2)); > } > break; > case INDEX_op_and_i64: > + a0 = args[0], a1 = args[1], a2 = args[2]; > if (const_args[2]) { > - tcg_out_andi64(s, args[0], args[1], args[2]); > + tcg_out_andi64(s, a0, a1, a2); > } else { > - tcg_out32(s, AND | SAB(args[1], args[0], args[2])); > + tcg_out32(s, AND | SAB(a1, a0, a2)); > } > break; > case INDEX_op_or_i64: > @@ -1420,14 +1422,36 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, > } > break; > case INDEX_op_andc_i32: > + a0 = args[0], a1 = args[1], a2 = args[2]; > + if (const_args[2]) { > + tcg_out_andi32(s, a0, a1, ~a2); > + } else { > + tcg_out32(s, ANDC | SAB(a1, a0, a2)); > + } > + break; > case INDEX_op_andc_i64: > - tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); > + a0 = args[0], a1 = args[1], a2 = args[2]; > + if (const_args[2]) { > + tcg_out_andi64(s, a0, a1, ~a2); > + } else { > + tcg_out32(s, ANDC | SAB(a1, a0, a2)); > + } > break; > case INDEX_op_orc_i32: > + if (const_args[2]) { > + tcg_out_ori32(s, args[0], args[1], ~args[2]); > + break; > + } > + /* FALLTHRU */ > case INDEX_op_orc_i64: > tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); > break; > case INDEX_op_eqv_i32: > + if (const_args[2]) { > + tcg_out_xori32(s, args[0], args[1], ~args[2]); > + break; > + } > + /* FALLTHRU */ > case INDEX_op_eqv_i64: > tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); > break; > @@ -1812,9 +1836,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { > { INDEX_op_and_i32, { "r", "r", "ri" } }, > { INDEX_op_or_i32, { "r", "r", "ri" } }, > { INDEX_op_xor_i32, { "r", "r", "ri" } }, > - { INDEX_op_andc_i32, { "r", "r", "r" } }, > - { INDEX_op_orc_i32, { "r", "r", "r" } }, > - { INDEX_op_eqv_i32, { "r", "r", "r" } }, > + { INDEX_op_andc_i32, { "r", "r", "ri" } }, > + { INDEX_op_orc_i32, { "r", "r", "ri" } }, > + { INDEX_op_eqv_i32, { "r", "r", "ri" } }, > { INDEX_op_nand_i32, { "r", "r", "r" } }, > { INDEX_op_nor_i32, { "r", "r", "r" } }, > > @@ -1832,10 +1856,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { > > { INDEX_op_add_i64, { "r", "r", "rTU" } }, > { INDEX_op_sub_i64, { "r", "rI", "rTU" } }, > - { INDEX_op_and_i64, { "r", "r", "rU" } }, > + { INDEX_op_and_i64, { "r", "r", "ri" } }, > { INDEX_op_or_i64, { "r", "r", "rU" } }, > { INDEX_op_xor_i64, { "r", "r", "rU" } }, > - { INDEX_op_andc_i64, { "r", "r", "r" } }, > + { INDEX_op_andc_i64, { "r", "r", "ri" } }, > { INDEX_op_orc_i64, { "r", "r", "r" } }, > { INDEX_op_eqv_i64, { "r", "r", "r" } }, > { INDEX_op_nand_i64, { "r", "r", "r" } }, Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Patch
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index a1be15a..c1d974b 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1388,17 +1388,19 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_and_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tcg_out_andi32(s, args[0], args[1], args[2]); + tcg_out_andi32(s, a0, a1, a2); } else { - tcg_out32(s, AND | SAB(args[1], args[0], args[2])); + tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_and_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - tcg_out_andi64(s, args[0], args[1], args[2]); + tcg_out_andi64(s, a0, a1, a2); } else { - tcg_out32(s, AND | SAB(args[1], args[0], args[2])); + tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_or_i64: @@ -1420,14 +1422,36 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_andc_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi32(s, a0, a1, ~a2); + } else { + tcg_out32(s, ANDC | SAB(a1, a0, a2)); + } + break; case INDEX_op_andc_i64: - tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out_andi64(s, a0, a1, ~a2); + } else { + tcg_out32(s, ANDC | SAB(a1, a0, a2)); + } break; case INDEX_op_orc_i32: + if (const_args[2]) { + tcg_out_ori32(s, args[0], args[1], ~args[2]); + break; + } + /* FALLTHRU */ case INDEX_op_orc_i64: tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); break; case INDEX_op_eqv_i32: + if (const_args[2]) { + tcg_out_xori32(s, args[0], args[1], ~args[2]); + break; + } + /* FALLTHRU */ case INDEX_op_eqv_i64: tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); break; @@ -1812,9 +1836,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_and_i32, { "r", "r", "ri" } }, { INDEX_op_or_i32, { "r", "r", "ri" } }, { INDEX_op_xor_i32, { "r", "r", "ri" } }, - { INDEX_op_andc_i32, { "r", "r", "r" } }, - { INDEX_op_orc_i32, { "r", "r", "r" } }, - { INDEX_op_eqv_i32, { "r", "r", "r" } }, + { INDEX_op_andc_i32, { "r", "r", "ri" } }, + { INDEX_op_orc_i32, { "r", "r", "ri" } }, + { INDEX_op_eqv_i32, { "r", "r", "ri" } }, { INDEX_op_nand_i32, { "r", "r", "r" } }, { INDEX_op_nor_i32, { "r", "r", "r" } }, @@ -1832,10 +1856,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_add_i64, { "r", "r", "rTU" } }, { INDEX_op_sub_i64, { "r", "rI", "rTU" } }, - { INDEX_op_and_i64, { "r", "r", "rU" } }, + { INDEX_op_and_i64, { "r", "r", "ri" } }, { INDEX_op_or_i64, { "r", "r", "rU" } }, { INDEX_op_xor_i64, { "r", "r", "rU" } }, - { INDEX_op_andc_i64, { "r", "r", "r" } }, + { INDEX_op_andc_i64, { "r", "r", "ri" } }, { INDEX_op_orc_i64, { "r", "r", "r" } }, { INDEX_op_eqv_i64, { "r", "r", "r" } }, { INDEX_op_nand_i64, { "r", "r", "r" } },
Since we have special code to handle and/or/xor with a constant, apply the same to andc/orc/eqv with a constant. Signed-off-by: Richard Henderson <rth@twiddle.net> --- tcg/ppc64/tcg-target.c | 44 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 10 deletions(-)