Patchwork [v2,18/27] tcg-ppc64: Implement compound logicals

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Submitter Richard Henderson
Date March 5, 2013, 12:33 a.m.
Message ID <1362443590-28191-19-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/224871/
State New
Headers show

Comments

Richard Henderson - March 5, 2013, 12:33 a.m.
Mostly copied from the ppc32 port.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc64/tcg-target.c | 34 ++++++++++++++++++++++++++++++++++
 tcg/ppc64/tcg-target.h | 20 ++++++++++----------
 2 files changed, 44 insertions(+), 10 deletions(-)
Aurelien Jarno - April 1, 2013, 2:58 p.m.
On Mon, Mar 04, 2013 at 04:33:01PM -0800, Richard Henderson wrote:
> Mostly copied from the ppc32 port.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/ppc64/tcg-target.c | 34 ++++++++++++++++++++++++++++++++++
>  tcg/ppc64/tcg-target.h | 20 ++++++++++----------
>  2 files changed, 44 insertions(+), 10 deletions(-)
> 
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index 576effc..a1be15a 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -385,6 +385,10 @@ static int tcg_target_const_match (tcg_target_long val,
>  #define NOR    XO31(124)
>  #define CNTLZW XO31( 26)
>  #define CNTLZD XO31( 58)
> +#define ANDC   XO31( 60)
> +#define ORC    XO31(412)
> +#define EQV    XO31(284)
> +#define NAND   XO31(476)
>  
>  #define MULLD  XO31(233)
>  #define MULHD  XO31( 73)
> @@ -1415,6 +1419,26 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
>              tcg_out32(s, XOR | SAB(a1, a0, a2));
>          }
>          break;
> +    case INDEX_op_andc_i32:
> +    case INDEX_op_andc_i64:
> +        tcg_out32(s, ANDC | SAB(args[1], args[0], args[2]));
> +        break;
> +    case INDEX_op_orc_i32:
> +    case INDEX_op_orc_i64:
> +        tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
> +        break;
> +    case INDEX_op_eqv_i32:
> +    case INDEX_op_eqv_i64:
> +        tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
> +        break;
> +    case INDEX_op_nand_i32:
> +    case INDEX_op_nand_i64:
> +        tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
> +        break;
> +    case INDEX_op_nor_i32:
> +    case INDEX_op_nor_i64:
> +        tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
> +        break;
>  
>      case INDEX_op_mul_i32:
>          if (const_args[2]) {
> @@ -1788,6 +1812,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>      { INDEX_op_and_i32, { "r", "r", "ri" } },
>      { INDEX_op_or_i32, { "r", "r", "ri" } },
>      { INDEX_op_xor_i32, { "r", "r", "ri" } },
> +    { INDEX_op_andc_i32, { "r", "r", "r" } },
> +    { INDEX_op_orc_i32, { "r", "r", "r" } },
> +    { INDEX_op_eqv_i32, { "r", "r", "r" } },
> +    { INDEX_op_nand_i32, { "r", "r", "r" } },
> +    { INDEX_op_nor_i32, { "r", "r", "r" } },
>  
>      { INDEX_op_shl_i32, { "r", "r", "ri" } },
>      { INDEX_op_shr_i32, { "r", "r", "ri" } },
> @@ -1806,6 +1835,11 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>      { INDEX_op_and_i64, { "r", "r", "rU" } },
>      { INDEX_op_or_i64, { "r", "r", "rU" } },
>      { INDEX_op_xor_i64, { "r", "r", "rU" } },
> +    { INDEX_op_andc_i64, { "r", "r", "r" } },
> +    { INDEX_op_orc_i64, { "r", "r", "r" } },
> +    { INDEX_op_eqv_i64, { "r", "r", "r" } },
> +    { INDEX_op_nand_i64, { "r", "r", "r" } },
> +    { INDEX_op_nor_i64, { "r", "r", "r" } },
>  
>      { INDEX_op_shl_i64, { "r", "r", "ri" } },
>      { INDEX_op_shr_i64, { "r", "r", "ri" } },
> diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
> index d8e1820..35414cf 100644
> --- a/tcg/ppc64/tcg-target.h
> +++ b/tcg/ppc64/tcg-target.h
> @@ -82,11 +82,11 @@ typedef enum {
>  #define TCG_TARGET_HAS_bswap32_i32      1
>  #define TCG_TARGET_HAS_not_i32          1
>  #define TCG_TARGET_HAS_neg_i32          1
> -#define TCG_TARGET_HAS_andc_i32         0
> -#define TCG_TARGET_HAS_orc_i32          0
> -#define TCG_TARGET_HAS_eqv_i32          0
> -#define TCG_TARGET_HAS_nand_i32         0
> -#define TCG_TARGET_HAS_nor_i32          0
> +#define TCG_TARGET_HAS_andc_i32         1
> +#define TCG_TARGET_HAS_orc_i32          1
> +#define TCG_TARGET_HAS_eqv_i32          1
> +#define TCG_TARGET_HAS_nand_i32         1
> +#define TCG_TARGET_HAS_nor_i32          1
>  #define TCG_TARGET_HAS_deposit_i32      0
>  #define TCG_TARGET_HAS_movcond_i32      0
>  #define TCG_TARGET_HAS_add2_i32         0
> @@ -105,11 +105,11 @@ typedef enum {
>  #define TCG_TARGET_HAS_bswap64_i64      1
>  #define TCG_TARGET_HAS_not_i64          1
>  #define TCG_TARGET_HAS_neg_i64          1
> -#define TCG_TARGET_HAS_andc_i64         0
> -#define TCG_TARGET_HAS_orc_i64          0
> -#define TCG_TARGET_HAS_eqv_i64          0
> -#define TCG_TARGET_HAS_nand_i64         0
> -#define TCG_TARGET_HAS_nor_i64          0
> +#define TCG_TARGET_HAS_andc_i64         1
> +#define TCG_TARGET_HAS_orc_i64          1
> +#define TCG_TARGET_HAS_eqv_i64          1
> +#define TCG_TARGET_HAS_nand_i64         1
> +#define TCG_TARGET_HAS_nor_i64          1
>  #define TCG_TARGET_HAS_deposit_i64      0
>  #define TCG_TARGET_HAS_movcond_i64      0
>  #define TCG_TARGET_HAS_add2_i64         0

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

Patch

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 576effc..a1be15a 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -385,6 +385,10 @@  static int tcg_target_const_match (tcg_target_long val,
 #define NOR    XO31(124)
 #define CNTLZW XO31( 26)
 #define CNTLZD XO31( 58)
+#define ANDC   XO31( 60)
+#define ORC    XO31(412)
+#define EQV    XO31(284)
+#define NAND   XO31(476)
 
 #define MULLD  XO31(233)
 #define MULHD  XO31( 73)
@@ -1415,6 +1419,26 @@  static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args,
             tcg_out32(s, XOR | SAB(a1, a0, a2));
         }
         break;
+    case INDEX_op_andc_i32:
+    case INDEX_op_andc_i64:
+        tcg_out32(s, ANDC | SAB(args[1], args[0], args[2]));
+        break;
+    case INDEX_op_orc_i32:
+    case INDEX_op_orc_i64:
+        tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
+        break;
+    case INDEX_op_eqv_i32:
+    case INDEX_op_eqv_i64:
+        tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
+        break;
+    case INDEX_op_nand_i32:
+    case INDEX_op_nand_i64:
+        tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
+        break;
+    case INDEX_op_nor_i32:
+    case INDEX_op_nor_i64:
+        tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
+        break;
 
     case INDEX_op_mul_i32:
         if (const_args[2]) {
@@ -1788,6 +1812,11 @@  static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_and_i32, { "r", "r", "ri" } },
     { INDEX_op_or_i32, { "r", "r", "ri" } },
     { INDEX_op_xor_i32, { "r", "r", "ri" } },
+    { INDEX_op_andc_i32, { "r", "r", "r" } },
+    { INDEX_op_orc_i32, { "r", "r", "r" } },
+    { INDEX_op_eqv_i32, { "r", "r", "r" } },
+    { INDEX_op_nand_i32, { "r", "r", "r" } },
+    { INDEX_op_nor_i32, { "r", "r", "r" } },
 
     { INDEX_op_shl_i32, { "r", "r", "ri" } },
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
@@ -1806,6 +1835,11 @@  static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_and_i64, { "r", "r", "rU" } },
     { INDEX_op_or_i64, { "r", "r", "rU" } },
     { INDEX_op_xor_i64, { "r", "r", "rU" } },
+    { INDEX_op_andc_i64, { "r", "r", "r" } },
+    { INDEX_op_orc_i64, { "r", "r", "r" } },
+    { INDEX_op_eqv_i64, { "r", "r", "r" } },
+    { INDEX_op_nand_i64, { "r", "r", "r" } },
+    { INDEX_op_nor_i64, { "r", "r", "r" } },
 
     { INDEX_op_shl_i64, { "r", "r", "ri" } },
     { INDEX_op_shr_i64, { "r", "r", "ri" } },
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index d8e1820..35414cf 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -82,11 +82,11 @@  typedef enum {
 #define TCG_TARGET_HAS_bswap32_i32      1
 #define TCG_TARGET_HAS_not_i32          1
 #define TCG_TARGET_HAS_neg_i32          1
-#define TCG_TARGET_HAS_andc_i32         0
-#define TCG_TARGET_HAS_orc_i32          0
-#define TCG_TARGET_HAS_eqv_i32          0
-#define TCG_TARGET_HAS_nand_i32         0
-#define TCG_TARGET_HAS_nor_i32          0
+#define TCG_TARGET_HAS_andc_i32         1
+#define TCG_TARGET_HAS_orc_i32          1
+#define TCG_TARGET_HAS_eqv_i32          1
+#define TCG_TARGET_HAS_nand_i32         1
+#define TCG_TARGET_HAS_nor_i32          1
 #define TCG_TARGET_HAS_deposit_i32      0
 #define TCG_TARGET_HAS_movcond_i32      0
 #define TCG_TARGET_HAS_add2_i32         0
@@ -105,11 +105,11 @@  typedef enum {
 #define TCG_TARGET_HAS_bswap64_i64      1
 #define TCG_TARGET_HAS_not_i64          1
 #define TCG_TARGET_HAS_neg_i64          1
-#define TCG_TARGET_HAS_andc_i64         0
-#define TCG_TARGET_HAS_orc_i64          0
-#define TCG_TARGET_HAS_eqv_i64          0
-#define TCG_TARGET_HAS_nand_i64         0
-#define TCG_TARGET_HAS_nor_i64          0
+#define TCG_TARGET_HAS_andc_i64         1
+#define TCG_TARGET_HAS_orc_i64          1
+#define TCG_TARGET_HAS_eqv_i64          1
+#define TCG_TARGET_HAS_nand_i64         1
+#define TCG_TARGET_HAS_nor_i64          1
 #define TCG_TARGET_HAS_deposit_i64      0
 #define TCG_TARGET_HAS_movcond_i64      0
 #define TCG_TARGET_HAS_add2_i64         0