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[50.194.63.110]) by mx.google.com with ESMTPS id ih1sm12171205igc.3.2013.03.04.16.33.30 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 04 Mar 2013 16:33:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 4 Mar 2013 16:32:52 -0800 Message-Id: <1362443590-28191-10-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1362443590-28191-1-git-send-email-rth@twiddle.net> References: <1362443590-28191-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:4001:c03::22a Cc: av1474@comtv.ru Subject: [Qemu-devel] [PATCH v2 09/27] tcg-ppc64: Rearrange integer constant constraints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We'll need a zero, and Z makes more sense for that. Make sure we have a full compliment of signed and unsigned 16 and 32-bit tests. Signed-off-by: Richard Henderson Reviewed-by: Aurelien Jarno --- tcg/ppc64/tcg-target.c | 43 +++++++++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 31b0cb7..0e4826d 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -22,7 +22,11 @@ * THE SOFTWARE. */ -#define TCG_CT_CONST_U32 0x100 +#define TCG_CT_CONST_S16 0x100 +#define TCG_CT_CONST_U16 0x200 +#define TCG_CT_CONST_S32 0x400 +#define TCG_CT_CONST_U32 0x800 +#define TCG_CT_CONST_ZERO 0x1000 static uint8_t *tb_ret_addr; @@ -242,9 +246,21 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) tcg_regset_reset_reg (ct->u.regs, TCG_REG_R6); #endif break; - case 'Z': + case 'I': + ct->ct |= TCG_CT_CONST_S16; + break; + case 'J': + ct->ct |= TCG_CT_CONST_U16; + break; + case 'T': + ct->ct |= TCG_CT_CONST_S32; + break; + case 'U': ct->ct |= TCG_CT_CONST_U32; break; + case 'Z': + ct->ct |= TCG_CT_CONST_ZERO; + break; default: return -1; } @@ -257,13 +273,20 @@ static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str) static int tcg_target_const_match (tcg_target_long val, const TCGArgConstraint *arg_ct) { - int ct; - - ct = arg_ct->ct; - if (ct & TCG_CT_CONST) + int ct = arg_ct->ct; + if (ct & TCG_CT_CONST) { + return 1; + } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { + return 1; + } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { return 1; - else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val)) + } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { return 1; + } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { + return 1; + } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } return 0; } @@ -1607,9 +1630,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_add_i64, { "r", "r", "ri" } }, { INDEX_op_sub_i64, { "r", "r", "ri" } }, - { INDEX_op_and_i64, { "r", "r", "rZ" } }, - { INDEX_op_or_i64, { "r", "r", "rZ" } }, - { INDEX_op_xor_i64, { "r", "r", "rZ" } }, + { INDEX_op_and_i64, { "r", "r", "rU" } }, + { INDEX_op_or_i64, { "r", "r", "rU" } }, + { INDEX_op_xor_i64, { "r", "r", "rU" } }, { INDEX_op_shl_i64, { "r", "r", "ri" } }, { INDEX_op_shr_i64, { "r", "r", "ri" } },