Patchwork [2/2] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC

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Submitter Jingoo Han
Date March 4, 2013, 10:23 a.m.
Message ID <016c01ce18c2$59bf89d0$0d3e9d70$%han@samsung.com>
Download mbox | patch
Permalink /patch/224679/
State Not Applicable
Headers show

Comments

Jingoo Han - March 4, 2013, 10:23 a.m.
Exynos5440 has two PCIe controllers which can be used as root complex
for PCIe interface.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
---
 arch/arm/boot/dts/exynos5440-ssdk5440.dts |    8 +++++++
 arch/arm/boot/dts/exynos5440.dtsi         |   32 +++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+), 0 deletions(-)

Patch

diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index 81e2c96..ecf6906 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -43,4 +43,12 @@ 
 	rtc {
 		status = "disabled";
 	};
+
+	pcie0@40000000 {
+		reset-gpio = <5>;
+	};
+
+	pcie1@60000000 {
+		reset-gpio = <22>;
+	};
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 0bde96d..16bb994 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -151,4 +151,36 @@ 
 		reg = <0x130000 0x1000>;
 		interrupts = <0 17 0>, <0 16 0>;
 	};
+
+	pcie0@40000000 {
+		compatible = "samsung,pcie-host";
+		reg = <0x40000000 0x4000
+			0x290000 0x1000
+			0x270000 0x1000
+			0x271000 0x40>;
+		interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+		pcie-host,io_size = <0x4000>;
+		pcie-host,cfg0_size = <0x100000>;
+		pcie-host,cfg1_size = <0x100000>;
+		pcie-host,mem_size = <0x10000000>;
+		pcie-host,in_mem_size = <0x8000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	pcie1@60000000 {
+		compatible = "samsung,pcie-host";
+		reg = <0x60000000 0x4000
+			0x2a0000 0x1000
+			0x272000 0x1000
+			0x271040 0x40>;
+		interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+		pcie-host,io_size = <0x4000>;
+		pcie-host,cfg0_size = <0x100000>;
+		pcie-host,cfg1_size = <0x100000>;
+		pcie-host,mem_size = <0x10000000>;
+		pcie-host,in_mem_size = <0x8000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
 };