From patchwork Mon Mar 4 09:01:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 224645 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4DBEF2C030D for ; Mon, 4 Mar 2013 20:07:45 +1100 (EST) Received: from localhost ([::1]:51686 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCRN1-0001oN-CQ for incoming@patchwork.ozlabs.org; Mon, 04 Mar 2013 04:07:43 -0500 Received: from eggs.gnu.org ([208.118.235.92]:38098) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCRMX-0001WE-JC for qemu-devel@nongnu.org; Mon, 04 Mar 2013 04:07:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCRMS-00081k-67 for qemu-devel@nongnu.org; Mon, 04 Mar 2013 04:07:13 -0500 Received: from mail-da0-f52.google.com ([209.85.210.52]:35423) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCRMR-00081S-Vf for qemu-devel@nongnu.org; Mon, 04 Mar 2013 04:07:08 -0500 Received: by mail-da0-f52.google.com with SMTP id x33so2453306dad.39 for ; Mon, 04 Mar 2013 01:07:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:in-reply-to:references:x-gm-message-state; bh=HDJf65JdyfuN5znppbdKl2t6Rn4aVpgWbR2iyK4oUao=; b=NXToZJM+N0V1ylEzVF7U3AKTXaFqHGh4UmiHXNtPN5h+bWEFLXD6xJQNaHYqj0AkaM F6vtScHgXFEGGkBoF++RoCniwNUqo1wQtJaISWh8kd9IJMEiNzHeIRUHZeSROz7H6gTO cHkwrAm4JWbXtJ4OLqHInfq9bEP0q7uUTC+cHt9dwfLvKCj94Ooj+XwfUoa0BLqUkFWa kzj+b5awI1z5AnhO7vULzL+rxFbRgQX3w4cRh6sZKAMWIFW1bAcdGyd+TkpTvWkSJici OaN4BUS1/WKWFpXuBaaULQDeqKGoxYy2cSkr55gEg98aKuCvTBnzG4X1zAthp0uxmoyv EOgw== X-Received: by 10.66.27.241 with SMTP id w17mr31398998pag.59.1362388027357; Mon, 04 Mar 2013 01:07:07 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id wm3sm21678932pbc.4.2013.03.04.01.07.05 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 04 Mar 2013 01:07:06 -0800 (PST) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Mon, 4 Mar 2013 19:01:39 +1000 Message-Id: <0cd7b312706e95d9619b2d3de4f4fa062bef6b9d.1362387546.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQkylBd1JoEM7Z1O2KgBbTXH/u10/FFjbaK1xWQYBlEJJU9zqYE4cjOoiwWvepGaWNakzvGN X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.210.52 Cc: "Peter A. G. Crosthwaite" , andreas.faerber@suse.de, dantesu@faraday-tech.com Subject: [Qemu-devel] [RFC PATCH v1 7/7] zynq_slcr: Implement CPU reset and halting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter A. G. Crosthwaite Implement the CPU reset and halt functions of the A9_CPU_RST_CTRL register (offset 0x244). Signed-off-by: Peter A. G. Crosthwaite --- changed from v2: used device halting API instead of talking to the cpu. hw/zynq_slcr.c | 19 +++++++++++++++++++ 1 files changed, 19 insertions(+), 0 deletions(-) diff --git a/hw/zynq_slcr.c b/hw/zynq_slcr.c index 4925358..945355e 100644 --- a/hw/zynq_slcr.c +++ b/hw/zynq_slcr.c @@ -116,6 +116,9 @@ typedef enum { RESET_MAX } ResetValues; +#define A9_CPU_RST_CTRL_RST_SHIFT 0 +#define A9_CPU_RST_CTRL_CLKSTOP_SHIFT 4 + typedef struct { SysBusDevice busdev; MemoryRegion iomem; @@ -346,6 +349,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { ZynqSLCRState *s = (ZynqSLCRState *)opaque; + int i; DB_PRINT("offset: %08x data: %08x\n", (unsigned)offset, (unsigned)val); @@ -400,6 +404,21 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, goto bad_reg; } s->reset[(offset - 0x200) / 4] = val; + if (offset - 0x200 == A9_CPU * 4) { /* CPU Reset */ + for (i = 0; i < NUM_CPUS && s->cpus[i]; ++i) { + bool is_rst = val & (1 << (A9_CPU_RST_CTRL_RST_SHIFT + i)); + bool is_clkstop = val & + (1 << (A9_CPU_RST_CTRL_CLKSTOP_SHIFT + i)); + if (is_rst) { + DB_PRINT("resetting cpu %d\n", i); + device_reset(s->cpus[i]); + } + DB_PRINT("%shalting cpu %d\n", is_rst || is_clkstop ? + "" : "un", i); + (is_rst || is_clkstop ? + device_halt : device_unhalt)(s->cpus[i]); + } + } break; case 0x300: s->apu_ctrl = val;