From patchwork Mon Mar 4 09:01:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 224644 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E86EF2C030D for ; Mon, 4 Mar 2013 20:07:05 +1100 (EST) Received: from localhost ([::1]:49926 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCRMK-0000qr-VL for incoming@patchwork.ozlabs.org; Mon, 04 Mar 2013 04:07:00 -0500 Received: from eggs.gnu.org ([208.118.235.92]:37929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCRLy-0000iK-12 for qemu-devel@nongnu.org; Mon, 04 Mar 2013 04:06:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UCRLs-0007uJ-Hp for qemu-devel@nongnu.org; Mon, 04 Mar 2013 04:06:37 -0500 Received: from mail-da0-f52.google.com ([209.85.210.52]:49673) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UCRLs-0007u4-Ak for qemu-devel@nongnu.org; Mon, 04 Mar 2013 04:06:32 -0500 Received: by mail-da0-f52.google.com with SMTP id x33so2447551dad.25 for ; Mon, 04 Mar 2013 01:06:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:in-reply-to:references:x-gm-message-state; bh=DlmKKDmpt9z31WrsRuFBOkQpriUFnMGLwq9c8XOrtMo=; b=J8ga4Ckv7MWI10JrlRbc608YhkLITAeHujNSaq3tYvRfilQtI9EBj26qsxF5B9X/r6 +s/1W2jdjj6VlWDKbZwkx6STaOBnEz/6m/9sLlFRkCHZkVkkyhG6IJQ1X/6h+8HMFDBF z9NP7RdtG8GWt1yDR3OTyQAc7hCpXlJEgC96S3FI/BmsULHreLZyyx+cOW153EuANuue yhj67o8ShxHl+QcOOBWf2owRJNquONYH4e/1UE1rtPHyd6PKcYFrGkcZ5+bGoMb5R2Bv UZG8VumPBIef5IaogLonNPjx7rMVUjul9rE4cp0/SpqFUMzsRKBLIxBzrnpZJpPCUwFU VDOQ== X-Received: by 10.68.218.100 with SMTP id pf4mr27010720pbc.156.1362387991657; Mon, 04 Mar 2013 01:06:31 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id c8sm21673492pbq.10.2013.03.04.01.06.29 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Mon, 04 Mar 2013 01:06:30 -0800 (PST) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Mon, 4 Mar 2013 19:01:38 +1000 Message-Id: <333ad6b5cb4fb0ce7894007af56ca9ac3bbd8884.1362387546.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQkBAvB9pUUiD52GYHk/4xhKm0ZbukBVnGssuHYs6ApOZAORZc4eD3aaXIlaaebxHaM+rUk+ X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.210.52 Cc: "Peter A. G. Crosthwaite" , andreas.faerber@suse.de, dantesu@faraday-tech.com Subject: [Qemu-devel] [RFC PATCH v1 6/7] zynq_slcr: Add links to the CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter A. G. Crosthwaite The SLCR needs to be able to reset the CPUs, so link the CPUs to the slcr. Signed-off-by: Peter A. G. Crosthwaite --- Changed from v2: Soften type of CPU to Device Looped link creator hw/xilinx_zynq.c | 7 +++++++ hw/zynq_slcr.c | 11 +++++++++++ 2 files changed, 18 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index 80a2777..9be2b3b 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -179,6 +179,13 @@ static void zynq_init(QEMUMachineInitArgs *args) dev = qdev_create(NULL, "xilinx,zynq_slcr"); qdev_init_nofail(dev); + Error *errp = NULL; + object_property_set_link(OBJECT(dev), OBJECT(cpus[0]), "cpu0", &errp); + assert_no_error(errp); + if (smp_cpus > 1) { + object_property_set_link(OBJECT(dev), OBJECT(cpus[1]), "cpu1", NULL); + assert_no_error(errp); + } sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); dev = qdev_create(NULL, "a9mpcore_priv"); diff --git a/hw/zynq_slcr.c b/hw/zynq_slcr.c index 27b00f0..4925358 100644 --- a/hw/zynq_slcr.c +++ b/hw/zynq_slcr.c @@ -19,6 +19,8 @@ #include "sysbus.h" #include "sysemu/sysemu.h" +#define NUM_CPUS 2 + #ifdef ZYNQ_ARM_SLCR_ERR_DEBUG #define DB_PRINT(...) do { \ fprintf(stderr, ": %s: ", __func__); \ @@ -118,6 +120,8 @@ typedef struct { SysBusDevice busdev; MemoryRegion iomem; + DeviceState *cpus[NUM_CPUS]; + union { struct { uint16_t scl; @@ -492,11 +496,18 @@ static const MemoryRegionOps slcr_ops = { static int zynq_slcr_init(SysBusDevice *dev) { + int i; ZynqSLCRState *s = FROM_SYSBUS(ZynqSLCRState, dev); memory_region_init_io(&s->iomem, &slcr_ops, s, "slcr", 0x1000); sysbus_init_mmio(dev, &s->iomem); + for (i = 0; i < NUM_CPUS; ++i) { + gchar *name = g_strdup_printf("cpu%d", i); + object_property_add_link(OBJECT(dev), name, TYPE_DEVICE, + (Object **) &s->cpus[i], NULL); + g_free(name); + } return 0; }