Patchwork [RFC,v1,4/7] sun4m: Use halting API to halt/unhalt CPUs

login
register
mail settings
Submitter Peter Crosthwaite
Date March 4, 2013, 9:01 a.m.
Message ID <7e289d2451695cfa9bea161ce19165f746e358ff.1362387546.git.peter.crosthwaite@xilinx.com>
Download mbox | patch
Permalink /patch/224642/
State New
Headers show

Comments

Peter Crosthwaite - March 4, 2013, 9:01 a.m.
Example for a change pattern that could be applied to use the halting API rather
than directly modifying the CPU halted bit.

Untested RFC.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 hw/sun4m.c |   24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)

Patch

diff --git a/hw/sun4m.c b/hw/sun4m.c
index d83d42c..b544782 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -261,8 +261,9 @@  static void cpu_kick_irq(SPARCCPU *cpu)
 {
     CPUSPARCState *env = &cpu->env;
     CPUState *cs = CPU(cpu);
+    DeviceState *d = DEVICE(cpu);
 
-    cs->halted = 0;
+    device_unhalt(d);
     cpu_check_irqs(env);
     qemu_cpu_kick(cs);
 }
@@ -289,20 +290,19 @@  static void dummy_cpu_set_irq(void *opaque, int irq, int level)
 
 static void main_cpu_reset(void *opaque)
 {
-    SPARCCPU *cpu = opaque;
-    CPUState *cs = CPU(cpu);
+    DeviceState *d = DEVICE(opaque);
 
-    cpu_reset(cs);
-    cs->halted = 0;
+    device_reset(d);
+    device_unhalt(d);
 }
 
 static void secondary_cpu_reset(void *opaque)
 {
-    SPARCCPU *cpu = opaque;
-    CPUState *cs = CPU(cpu);
+    DeviceState *d = DEVICE(opaque);
+
+    device_reset(d);
+    device_halt(d);
 
-    cpu_reset(cs);
-    cs->halted = 1;
 }
 
 static void cpu_halt_signal(void *opaque, int irq, int level)
@@ -833,7 +833,7 @@  static const TypeInfo ram_info = {
 static void cpu_devinit(const char *cpu_model, unsigned int id,
                         uint64_t prom_addr, qemu_irq **cpu_irqs)
 {
-    CPUState *cs;
+    DeviceState *d;
     SPARCCPU *cpu;
     CPUSPARCState *env;
 
@@ -849,8 +849,8 @@  static void cpu_devinit(const char *cpu_model, unsigned int id,
         qemu_register_reset(main_cpu_reset, cpu);
     } else {
         qemu_register_reset(secondary_cpu_reset, cpu);
-        cs = CPU(cpu);
-        cs->halted = 1;
+        d = DEVICE(cpu);
+        device_halt(DEIVCE(cpu));
     }
     *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
     env->prom_addr = prom_addr;