Message ID | 1362115578-12165-2-git-send-email-sjg@chromium.org |
---|---|
State | Accepted, archived |
Delegated to: | Simon Glass |
Headers | show |
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 6a23974..1a2f85c 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -228,3 +228,26 @@ void flush_dcache_range(unsigned long start, unsigned long stop) void invalidate_dcache_range(unsigned long start, unsigned long stop) { } + +void dcache_enable(void) +{ + enable_caches(); +} + +void dcache_disable(void) +{ + disable_caches(); +} + +void icache_enable(void) +{ +} + +void icache_disable(void) +{ +} + +int icache_status(void) +{ + return 1; +}
At present most x86 cache operations are undefined. Add a basic implementation for these. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: None arch/x86/cpu/cpu.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)