diff mbox

[16/17] cadence_gem: Don't reset rx desc pointer on rx_en

Message ID 1362077643-31443-17-git-send-email-peter.maydell@linaro.org
State New
Headers show

Commit Message

Peter Maydell Feb. 28, 2013, 6:54 p.m. UTC 
From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

This doesn't happen in the real hardware. The Zynq TRM explicitly states that
this bit has no effect on the rx descriptor pointer ("The receive queue
pointer register is unaffected").

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 06fdf92b78ee62d8965779bafd29c8df1a5d2718.1360901435.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/cadence_gem.c |    4 ----
 1 file changed, 4 deletions(-)
diff mbox

Patch

diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c
index a1ac069..61f1801 100644
--- a/hw/cadence_gem.c
+++ b/hw/cadence_gem.c
@@ -1083,10 +1083,6 @@  static void gem_write(void *opaque, hwaddr offset, uint64_t val,
             /* Reset to start of Q when transmit disabled. */
             s->tx_desc_addr = s->regs[GEM_TXQBASE];
         }
-        if (!(val & GEM_NWCTRL_RXENA)) {
-            /* Reset to start of Q when receive disabled. */
-            s->rx_desc_addr = s->regs[GEM_RXQBASE];
-        }
         if (val & GEM_NWCTRL_RXENA) {
             qemu_flush_queued_packets(qemu_get_queue(s->nic));
         }