| Submitter | Peter Maydell |
|---|---|
| Date | Feb. 28, 2013, 6:53 p.m. |
| Message ID | <1362077643-31443-14-git-send-email-peter.maydell@linaro.org> |
| Download | mbox | patch |
| Permalink | /patch/224152/ |
| State | New |
| Headers | show |
Comments
Patch
diff --git a/hw/cadence_gem.c b/hw/cadence_gem.c index ab86c17..e6032ea 100644 --- a/hw/cadence_gem.c +++ b/hw/cadence_gem.c @@ -1106,6 +1106,9 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, /* Reset to start of Q when receive disabled. */ s->rx_desc_addr = s->regs[GEM_RXQBASE]; } + if (val & GEM_NWCTRL_RXENA) { + qemu_flush_queued_packets(qemu_get_queue(s->nic)); + } break; case GEM_TXSTATUS: