Patchwork [U-Boot,9/9,v2] Exynos: pwm: Use generic api to get pwm clk freq

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Submitter Akshay Saraswat
Date Feb. 28, 2013, 10:59 a.m.
Message ID <1362049164-10297-10-git-send-email-akshay.s@samsung.com>
Download mbox | patch
Permalink /patch/223877/
State Changes Requested
Delegated to: Minkyu Kang
Headers show

Comments

Akshay Saraswat - Feb. 28, 2013, 10:59 a.m.
Use generic api to get the pwm clock frequency

Test with command "sf probe 1:0; time sf read 40008000 0 1000".
Try with different numbers of bytes and see that sane values are obtained
Build and boot U-boot with this patch, backlight works properly.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
---
Changes since v1:
        - Restored get_pwm_clk call in case of non-exynos5 cpu.

 arch/arm/cpu/armv7/s5p-common/pwm.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)
Simon Glass - Feb. 28, 2013, 1:40 p.m.
Hi Akshay,

On Thu, Feb 28, 2013 at 2:59 AM, Akshay Saraswat <akshay.s@samsung.com> wrote:
> Use generic api to get the pwm clock frequency
>
> Test with command "sf probe 1:0; time sf read 40008000 0 1000".
> Try with different numbers of bytes and see that sane values are obtained
> Build and boot U-boot with this patch, backlight works properly.

>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>

Acked-by: Simon Glass <sjg@chromium.org>

(I don't think SPI flash (the sf probe) is related to this test)

> ---
> Changes since v1:
>         - Restored get_pwm_clk call in case of non-exynos5 cpu.
>
>  arch/arm/cpu/armv7/s5p-common/pwm.c | 17 ++++++++++++++---
>  1 file changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c
> index 6f401b8..f5e9a95 100644
> --- a/arch/arm/cpu/armv7/s5p-common/pwm.c
> +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c
> @@ -28,6 +28,7 @@
>  #include <asm/io.h>
>  #include <asm/arch/pwm.h>
>  #include <asm/arch/clk.h>
> +#include <asm/arch/periph.h>
>
>  int pwm_enable(int pwm_id)
>  {
> @@ -60,7 +61,10 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
>         unsigned long tin_parent_rate;
>         unsigned int div;
>
> -       tin_parent_rate = get_pwm_clk();
> +       if (cpu_is_exynos5())
> +               tin_parent_rate = clock_get_periph_rate(PERIPH_ID_PWM0);
> +       else
> +               tin_parent_rate = get_pwm_clk();
>
>         for (div = 2; div <= 16; div *= 2) {
>                 if ((tin_parent_rate / (div << 16)) < freq)
> @@ -165,8 +169,15 @@ int pwm_init(int pwm_id, int div, int invert)
>                 ticks_per_period = -1UL;
>         } else {
>                 const unsigned long pwm_hz = 1000;
> -               unsigned long timer_rate_hz = get_pwm_clk() /
> -                       ((prescaler + 1) * (1 << div));
> +               unsigned long timer_rate_hz;
> +
> +               if (cpu_is_exynos5()) {
> +                       timer_rate_hz = clock_get_periph_rate(PERIPH_ID_PWM0)
> +                                       / ((prescaler + 1) * (1 << div));
> +               } else {
> +                       timer_rate_hz = get_pwm_clk() /
> +                               ((prescaler + 1) * (1 << div));
> +               }
>
>                 ticks_per_period = timer_rate_hz / pwm_hz;
>         }
> --
> 1.8.0
>

Patch

diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c
index 6f401b8..f5e9a95 100644
--- a/arch/arm/cpu/armv7/s5p-common/pwm.c
+++ b/arch/arm/cpu/armv7/s5p-common/pwm.c
@@ -28,6 +28,7 @@ 
 #include <asm/io.h>
 #include <asm/arch/pwm.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/periph.h>
 
 int pwm_enable(int pwm_id)
 {
@@ -60,7 +61,10 @@  static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
 	unsigned long tin_parent_rate;
 	unsigned int div;
 
-	tin_parent_rate = get_pwm_clk();
+	if (cpu_is_exynos5())
+		tin_parent_rate = clock_get_periph_rate(PERIPH_ID_PWM0);
+	else
+		tin_parent_rate = get_pwm_clk();
 
 	for (div = 2; div <= 16; div *= 2) {
 		if ((tin_parent_rate / (div << 16)) < freq)
@@ -165,8 +169,15 @@  int pwm_init(int pwm_id, int div, int invert)
 		ticks_per_period = -1UL;
 	} else {
 		const unsigned long pwm_hz = 1000;
-		unsigned long timer_rate_hz = get_pwm_clk() /
-			((prescaler + 1) * (1 << div));
+		unsigned long timer_rate_hz;
+
+		if (cpu_is_exynos5()) {
+			timer_rate_hz = clock_get_periph_rate(PERIPH_ID_PWM0)
+					/ ((prescaler + 1) * (1 << div));
+		} else {
+			timer_rate_hz = get_pwm_clk() /
+				((prescaler + 1) * (1 << div));
+		}
 
 		ticks_per_period = timer_rate_hz / pwm_hz;
 	}