Patchwork [committed] Fix PR 45472

login
register
mail settings
Submitter Andrey Belevantsev
Date Feb. 27, 2013, 9:03 a.m.
Message ID <512DCBE3.1070507@ispras.ru>
Download mbox | patch
Permalink /patch/223557/
State New
Headers show

Comments

Andrey Belevantsev - Feb. 27, 2013, 9:03 a.m.
Hello,

For this volatile-related issue (no volatile bits on volatile fields of a 
non-volatile struct) AFAIU there is an agreement of fixing the front-ends 
if needed, but anyways the patch to the selective scheduler is required 
that properly merges expressions so that the may_trap_p bit is preserved.

So the following patch was successfully tested on ia64 and x86-64, approved 
by Alexander offline, committed to trunk.  The patch needs backport to 
other branches in about two weeks.

Andrey

         PR middle-end/45472

     	gcc/
         * sel-sched-ir.c (merge_expr): Also change vinsn of merged expr
         when the may_trap_p bit of the exprs being merged differs.

         Reorder tests for speculativeness in the logical and operator.

     	testsuite/
     	* gcc.dg/45472.c: New test.
Andrey Belevantsev - April 1, 2013, 8:36 a.m.
On 27.02.2013 13:03, Andrey Belevantsev wrote:
> Hello,
>
> For this volatile-related issue (no volatile bits on volatile fields of a
> non-volatile struct) AFAIU there is an agreement of fixing the front-ends
> if needed, but anyways the patch to the selective scheduler is required
> that properly merges expressions so that the may_trap_p bit is preserved.
>
> So the following patch was successfully tested on ia64 and x86-64, approved
> by Alexander offline, committed to trunk.  The patch needs backport to
> other branches in about two weeks.
>
> Andrey
>
>          PR middle-end/45472
>
>          gcc/
>          * sel-sched-ir.c (merge_expr): Also change vinsn of merged expr
>          when the may_trap_p bit of the exprs being merged differs.
>
>          Reorder tests for speculativeness in the logical and operator.
>
>          testsuite/
>          * gcc.dg/45472.c: New test.

Now backported to 4.7 and 4.6 with Jakub's patch for the sel-sched-ir.c 
memory leak added.

Andrey
Index: gcc/ChangeLog
===================================================================
*** gcc/ChangeLog	(revision 197298)
--- gcc/ChangeLog	(revision 197299)
***************
*** 1,6 ****
--- 1,25 ----
  2013-04-01  Andrey Belevantsev  <abel@ispras.ru>
  
  	Backport from mainline
+ 	2013-02-27  Andrey Belevantsev  <abel@ispras.ru>
+ 
+ 	PR middle-end/45472
+ 	
+ 	* sel-sched-ir.c (merge_expr): Also change vinsn of merged expr
+ 	when the may_trap_p bit of the exprs being merged differs.
+ 	Reorder tests for speculativeness in the logical and operator.
+ 
+ 	Backport from mainline
+ 	 2013-03-05  Jakub Jelinek  <jakub@redhat.com>
+ 	 
+ 	PR middle-end/56461
+ 	* sel-sched-ir.c (free_sched_pools): Release
+ 	succs_info_pool.stack[succs_info_pool.max_top] vectors too
+ 	if succs_info_pool.max_top isn't -1.
+ 
+ 2013-04-01  Andrey Belevantsev  <abel@ispras.ru>
+ 
+ 	Backport from mainline
  	2012-02-19  Andrey Belevantsev  <abel@ispras.ru>
  
  	PR middle-end/55889
Index: gcc/testsuite/gcc.dg/pr45472.c
===================================================================
*** gcc/testsuite/gcc.dg/pr45472.c	(revision 0)
--- gcc/testsuite/gcc.dg/pr45472.c	(revision 197299)
***************
*** 0 ****
--- 1,63 ----
+ /* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+ /* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */
+ 
+ struct S
+ {
+   volatile long vl;
+   int i;
+ };
+ struct S s1, s2;
+ 
+ void
+ foo (int j, int c)
+ {
+   int i;
+   for (i = 0; i <= j; i++)
+     {
+       if (c)
+ 	s2.vl += s1.vl;
+       s1 = s2;
+     }
+ }
+ /* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+ /* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */
+ 
+ struct S
+ {
+   volatile long vl;
+   int i;
+ };
+ struct S s1, s2;
+ 
+ void
+ foo (int j, int c)
+ {
+   int i;
+   for (i = 0; i <= j; i++)
+     {
+       if (c)
+ 	s2.vl += s1.vl;
+       s1 = s2;
+     }
+ }
+ /* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+ /* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */
+ 
+ struct S
+ {
+   volatile long vl;
+   int i;
+ };
+ struct S s1, s2;
+ 
+ void
+ foo (int j, int c)
+ {
+   int i;
+   for (i = 0; i <= j; i++)
+     {
+       if (c)
+ 	s2.vl += s1.vl;
+       s1 = s2;
+     }
+ }
Index: gcc/testsuite/ChangeLog
===================================================================
*** gcc/testsuite/ChangeLog	(revision 197298)
--- gcc/testsuite/ChangeLog	(revision 197299)
***************
*** 1,3 ****
--- 1,11 ----
+ 2013-04-01  Andrey Belevantsev  <abel@ispras.ru>
+ 
+ 	Backport from mainline
+ 	2013-02-27  Andrey Belevantsev  <abel@ispras.ru>
+ 	
+ 	PR middle-end/45472
+ 	* gcc.dg/pr45472.c: New test.
+ 
  2013-03-26  Richard Biener  <rguenther@suse.de>
  
  	Backport from mainline
Index: gcc/sel-sched-ir.c
===================================================================
*** gcc/sel-sched-ir.c	(revision 197298)
--- gcc/sel-sched-ir.c	(revision 197299)
*************** merge_expr (expr_t to, expr_t from, insn
*** 1862,1869 ****
    /* Make sure that speculative pattern is propagated into exprs that
       have non-speculative one.  This will provide us with consistent
       speculative bits and speculative patterns inside expr.  */
!   if (EXPR_SPEC_DONE_DS (to) == 0
!       && EXPR_SPEC_DONE_DS (from) != 0)
      change_vinsn_in_expr (to, EXPR_VINSN (from));
  
    merge_expr_data (to, from, split_point);
--- 1862,1873 ----
    /* Make sure that speculative pattern is propagated into exprs that
       have non-speculative one.  This will provide us with consistent
       speculative bits and speculative patterns inside expr.  */
!   if ((EXPR_SPEC_DONE_DS (from) != 0
!        && EXPR_SPEC_DONE_DS (to) == 0)
!       /* Do likewise for volatile insns, so that we always retain
! 	 the may_trap_p bit on the resulting expression.  */
!       || (VINSN_MAY_TRAP_P (EXPR_VINSN (from))
! 	  && !VINSN_MAY_TRAP_P (EXPR_VINSN (to))))
      change_vinsn_in_expr (to, EXPR_VINSN (from));
  
    merge_expr_data (to, from, split_point);
*************** free_sched_pools (void)
*** 5019,5025 ****
  
    free_alloc_pool (sched_lists_pool);
    gcc_assert (succs_info_pool.top == -1);
!   for (i = 0; i < succs_info_pool.max_top; i++)
      {
        VEC_free (rtx, heap, succs_info_pool.stack[i].succs_ok);
        VEC_free (rtx, heap, succs_info_pool.stack[i].succs_other);
--- 5023,5029 ----
  
    free_alloc_pool (sched_lists_pool);
    gcc_assert (succs_info_pool.top == -1);
!   for (i = 0; i <= succs_info_pool.max_top; i++)
      {
        VEC_free (rtx, heap, succs_info_pool.stack[i].succs_ok);
        VEC_free (rtx, heap, succs_info_pool.stack[i].succs_other);

Patch

Index: gcc/testsuite/gcc.dg/pr45472.c
===================================================================
*** gcc/testsuite/gcc.dg/pr45472.c	(revision 0)
--- gcc/testsuite/gcc.dg/pr45472.c	(revision 196308)
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+ /* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */
+ 
+ struct S
+ {
+   volatile long vl;
+   int i;
+ };
+ struct S s1, s2;
+ 
+ void
+ foo (int j, int c)
+ {
+   int i;
+   for (i = 0; i <= j; i++)
+     {
+       if (c)
+ 	s2.vl += s1.vl;
+       s1 = s2;
+     }
+ }
Index: gcc/sel-sched-ir.c
===================================================================
*** gcc/sel-sched-ir.c	(revision 196307)
--- gcc/sel-sched-ir.c	(revision 196308)
*************** merge_expr (expr_t to, expr_t from, insn
*** 1866,1873 ****
    /* Make sure that speculative pattern is propagated into exprs that
       have non-speculative one.  This will provide us with consistent
       speculative bits and speculative patterns inside expr.  */
!   if (EXPR_SPEC_DONE_DS (to) == 0
!       && EXPR_SPEC_DONE_DS (from) != 0)
      change_vinsn_in_expr (to, EXPR_VINSN (from));
  
    merge_expr_data (to, from, split_point);
--- 1866,1877 ----
    /* Make sure that speculative pattern is propagated into exprs that
       have non-speculative one.  This will provide us with consistent
       speculative bits and speculative patterns inside expr.  */
!   if ((EXPR_SPEC_DONE_DS (from) != 0
!        && EXPR_SPEC_DONE_DS (to) == 0)
!       /* Do likewise for volatile insns, so that we always retain
! 	 the may_trap_p bit on the resulting expression.  */
!       || (VINSN_MAY_TRAP_P (EXPR_VINSN (from))
! 	  && !VINSN_MAY_TRAP_P (EXPR_VINSN (to))))
      change_vinsn_in_expr (to, EXPR_VINSN (from));
  
    merge_expr_data (to, from, split_point);