From patchwork Wed Feb 27 07:16:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 223530 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 00E932C007B for ; Wed, 27 Feb 2013 18:49:31 +1100 (EST) Received: from localhost ([::1]:51563 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UAblY-0001ft-Oi for incoming@patchwork.ozlabs.org; Wed, 27 Feb 2013 02:49:28 -0500 Received: from eggs.gnu.org ([208.118.235.92]:57787) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UAbG8-0007z9-52 for qemu-devel@nongnu.org; Wed, 27 Feb 2013 02:17:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UAbG5-000444-OK for qemu-devel@nongnu.org; Wed, 27 Feb 2013 02:17:00 -0500 Received: from mail-pa0-f42.google.com ([209.85.220.42]:53702) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UAbG5-00043r-Ib for qemu-devel@nongnu.org; Wed, 27 Feb 2013 02:16:57 -0500 Received: by mail-pa0-f42.google.com with SMTP id kq12so258928pab.1 for ; Tue, 26 Feb 2013 23:16:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=qwLJ5t5ExY5HbL7cTCDCmNb7sY0g9eLHB1DbWSMBbD0=; b=pN+rFfKel4dPINZihpWCGmQfGMSYSt6a8BaVhqepYrgT7g5yPu5xHIvAX2nB2R+8yi V70Oj1JWkfi7qwT1KuM8O4Bj1+Kc4gVMjcxiqK2Lc7SSX3qTV8docaWtFa5tFt2sCUn6 kCvKaF0KNPMkTn2Zcp6EyMBPRCLdaMHRo1eHItSz1nUyCC2CCikX43UqUHzqsST0arlt RAzewDr7Z+IRI/qjCvLiqBMz+e7SlHFJ0gafGCsJNuoWUk+DTF/pRO5qriEx1PmziG30 ppGK1pY5w/vLqSkxP6x7qZllz2YvXm6MBxZj8biylI8J69UW4Z8Ou9HX/tRcLvO+coUm IATA== X-Received: by 10.68.135.196 with SMTP id pu4mr1944502pbb.50.1361949416942; Tue, 26 Feb 2013 23:16:56 -0800 (PST) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPS id y10sm3686743pbf.39.2013.02.26.23.16.54 (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Tue, 26 Feb 2013 23:16:55 -0800 (PST) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Wed, 27 Feb 2013 17:16:16 +1000 Message-Id: <1361949376-25680-1-git-send-email-peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 X-Gm-Message-State: ALoCoQkgFeUwZOHvX7uVb0XU705/fddDHrvNHqutdFcXLWJp7AqdZ5NzLYNSjLEzJxyjrvRqxiDT X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.42 Cc: edgar.iglesias@gmail.com, Peter Crosthwaite , Nathan Rossi , peter.maydell@linaro.org Subject: [Qemu-devel] [PATCH] target-arm: Added CP15 VBAR support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Nathan Rossi Added Vector Base Address remapping on ARM v7. Signed-off-by: Nathan Rossi Signed-off-by: Peter Crosthwaite --- target-arm/cpu.h | 1 + target-arm/helper.c | 14 ++++++++++++++ target-arm/machine.c | 2 ++ 3 files changed, 17 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2902ba5..57ed2ee 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -138,6 +138,7 @@ typedef struct CPUARMState { uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ + uint32_t c12_vector_base_address; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_context; /* Context ID. */ uint32_t c13_tls1; /* User RW Thread register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index e97e1a5..db2e31d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -408,6 +408,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .resetvalue = 0, .writefn = pmintenclr_write }, + { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c12_vector_base_address), + .resetvalue = 0 }, { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), .resetvalue = 0, }, @@ -1892,7 +1896,17 @@ void do_interrupt(CPUARMState *env) } /* High vectors. */ if (env->cp15.c1_sys & (1 << 13)) { + /* when enabled, base address cannot be remapped. */ addr += 0xffff0000; + } else if (arm_feature(env, ARM_FEATURE_V7)) { + /* ARM v7 architectures provide a vector base address register to remap + * the interrupt vector table. + * This register is only followed in non-monitor mode, and has a secure + * and un-secure copy. Since the cpu is always in a un-secure operation + * and is never in monitor mode this feature is always active. + * Note: only bits 31:5 are valid. + */ + addr += env->cp15.c12_vector_base_address & 0xffffffe0; } switch_mode (env, new_mode); env->spsr = cpsr_read(env); diff --git a/target-arm/machine.c b/target-arm/machine.c index 68dca7f..2d07c51 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -53,6 +53,7 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->cp15.c9_pmxevtyper); qemu_put_be32(f, env->cp15.c9_pmuserenr); qemu_put_be32(f, env->cp15.c9_pminten); + qemu_put_be32(f, env->cp15.c12_vector_base_address); qemu_put_be32(f, env->cp15.c13_fcse); qemu_put_be32(f, env->cp15.c13_context); qemu_put_be32(f, env->cp15.c13_tls1); @@ -173,6 +174,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->cp15.c9_pmxevtyper = qemu_get_be32(f); env->cp15.c9_pmuserenr = qemu_get_be32(f); env->cp15.c9_pminten = qemu_get_be32(f); + env->cp15.c12_vector_base_address = qemu_get_be32(f); env->cp15.c13_fcse = qemu_get_be32(f); env->cp15.c13_context = qemu_get_be32(f); env->cp15.c13_tls1 = qemu_get_be32(f);