Patchwork [U-Boot,v1,6/6] blackfin: run core1 from L1 code sram start address in uboot init code on core 0

login
register
mail settings
Submitter Sonic Zhang
Date Feb. 27, 2013, 6:50 a.m.
Message ID <1361947807-27384-7-git-send-email-sonic.adi@gmail.com>
Download mbox | patch
Permalink /patch/223517/
State Accepted
Delegated to: Sonic Zhang
Headers show

Comments

Sonic Zhang - Feb. 27, 2013, 6:50 a.m.
From: Sonic Zhang <sonic.zhang@analog.com>

Define core 1 L1 code sram start address.
Add function to enable core 1 for BF609 and BF561.
Add config macro to allow customer to run core 1 in uboot init code on core 0.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
---
 arch/blackfin/cpu/cpu.c                          |   29 ++++++++++++++++++++++
 arch/blackfin/include/asm/mach-bf561/BF561_def.h |    2 +
 arch/blackfin/include/asm/mach-bf609/BF609_def.h |    2 +
 include/configs/bf561-ezkit.h                    |    5 ++++
 include/configs/bf609-ezkit.h                    |    5 ++++
 5 files changed, 43 insertions(+), 0 deletions(-)

Patch

diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c
index b9fdb07..d841f64 100644
--- a/arch/blackfin/cpu/cpu.c
+++ b/arch/blackfin/cpu/cpu.c
@@ -23,6 +23,31 @@ 
 
 ulong bfin_poweron_retx;
 
+#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
+void bfin_core1_start(void)
+{
+#ifdef BF561_FAMILY
+	/* Enable core 1 */
+	bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
+#else
+	/* Enable core 1 */
+	bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START);
+	bfin_write32(RCU0_CRCTL, 0);
+
+	bfin_write32(RCU0_CRCTL, 0x2);
+
+	/* Check if core 1 starts */
+	while (!(bfin_read32(RCU0_CRSTAT) & 0x2))
+		continue;
+
+	bfin_write32(RCU0_CRCTL, 0);
+
+	/* flag to notify cces core 1 application */
+	bfin_write32(SDU0_MSG_SET, (1 << 19));
+#endif
+}
+#endif
+
 __attribute__ ((__noreturn__))
 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 {
@@ -73,6 +98,10 @@  void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
 # endif
 #endif
 
+#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
+	bfin_core1_start();
+#endif
+
 	serial_early_puts("Board init flash\n");
 	board_init_f(bootflag);
 }
diff --git a/arch/blackfin/include/asm/mach-bf561/BF561_def.h b/arch/blackfin/include/asm/mach-bf561/BF561_def.h
index a7ff5a3..8fd552f 100644
--- a/arch/blackfin/include/asm/mach-bf561/BF561_def.h
+++ b/arch/blackfin/include/asm/mach-bf561/BF561_def.h
@@ -714,4 +714,6 @@ 
 #define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1)
 #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
 
+#define COREB_L1_CODE_START       0xFF600000
+
 #endif /* __BFIN_DEF_ADSP_BF561_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
index 0fb0fdf..15016db 100644
--- a/arch/blackfin/include/asm/mach-bf609/BF609_def.h
+++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
@@ -238,4 +238,6 @@ 
 #define L1_INST_SRAM_SIZE 0x8000
 #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
 
+#define COREB_L1_CODE_START       0xFF600000
+
 #endif /* __BFIN_DEF_ADSP_BF609_proc__ */
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 1a9d27e..6ee1e4c 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -98,6 +98,11 @@ 
  */
 #define CONFIG_UART_CONSOLE	0
 
+/*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN	1 */
+
 
 /*
  * Pull in common ADI header for remaining command/environment setup
diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h
index 02149fa..8b90129 100644
--- a/include/configs/bf609-ezkit.h
+++ b/include/configs/bf609-ezkit.h
@@ -156,6 +156,11 @@ 
 #endif
 
 /*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN	1 */
+
+/*
  * Pull in common ADI header for remaining command/environment setup
  */
 #include <configs/bfin_adi_common.h>