From patchwork Tue Feb 26 09:13:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuo-Jung Su X-Patchwork-Id: 223179 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D69A02C0306 for ; Tue, 26 Feb 2013 21:21:06 +1100 (EST) Received: from localhost ([::1]:51733 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UAGdD-0001sy-3d for incoming@patchwork.ozlabs.org; Tue, 26 Feb 2013 04:15:27 -0500 Received: from eggs.gnu.org ([208.118.235.92]:34351) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UAGcr-00019C-C0 for qemu-devel@nongnu.org; Tue, 26 Feb 2013 04:15:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UAGci-0005LN-DR for qemu-devel@nongnu.org; Tue, 26 Feb 2013 04:15:05 -0500 Received: from mail-pb0-f48.google.com ([209.85.160.48]:35940) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UAGci-0005Kx-2T for qemu-devel@nongnu.org; Tue, 26 Feb 2013 04:14:56 -0500 Received: by mail-pb0-f48.google.com with SMTP id wy12so2238369pbc.7 for ; Tue, 26 Feb 2013 01:14:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=b5nCdnrragcmbNYzJFc26B7ouheKEXRqE7VH8sh3Tlk=; b=aey7RfJlfkNqfIl1JeX3SD11KMJiuJpjYliFMx6QohrNpZqUwfS50bh4vujRHYb8Ct tE8t8cziEkDS6DW0Y8RyOp8NpmmCvYBl/itDuxV23o8wLYqL/C3beEKAotaOFZgvxh2e EEaBSHyUu6PBIR+jKtRLJZgzg6w4A+towus6LvIf65ChlXdF7XLuOTJicUbW8t0LADId n/G+Rp7ZpU2vLPpzZdCvUHcNuEbZWcrfxAcCnar+kQ2rqaunnqFTf+zGLArIzeA2MIry PE1+CTApIjxldEXv5NVduDyRnrg7DNSIk4DlLYWtmSxputDwyETBIyYZgZqLg1TGjAm/ Kh4g== X-Received: by 10.68.143.74 with SMTP id sc10mr22395580pbb.110.1361870095377; Tue, 26 Feb 2013 01:14:55 -0800 (PST) Received: from localhost.localdomain ([220.132.37.35]) by mx.google.com with ESMTPS id t4sm823747pax.0.2013.02.26.01.14.52 (version=TLSv1 cipher=DES-CBC3-SHA bits=168/168); Tue, 26 Feb 2013 01:14:54 -0800 (PST) From: Kuo-Jung Su To: qemu-devel@nongnu.org Date: Tue, 26 Feb 2013 17:13:57 +0800 Message-Id: <1361870054-18564-7-git-send-email-dantesu@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1361870054-18564-1-git-send-email-dantesu@gmail.com> References: <1361870054-18564-1-git-send-email-dantesu@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.160.48 Cc: Peter Maydell , i.mitsyanko@samsung.com, Blue Swirl , Paul Brook , Kuo-Jung Su , Andreas , fred.konrad@greensocs.com Subject: [Qemu-devel] [PATCH v4 06/23] hw/arm: add Faraday FTPWMTMR010 timer support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Kuo-Jung Su The FTPWMTMR010 is an APB device which provides up to 8 independent timers. Signed-off-by: Kuo-Jung Su --- hw/arm/Makefile.objs | 1 + hw/arm/faraday_a369_soc.c | 10 ++ hw/arm/ftpwmtmr010.c | 257 +++++++++++++++++++++++++++++++++++++++++++++ hw/arm/ftpwmtmr010.h | 29 +++++ 4 files changed, 297 insertions(+) create mode 100644 hw/arm/ftpwmtmr010.c create mode 100644 hw/arm/ftpwmtmr010.h diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 2a4c7d6..5adf9c2 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -40,3 +40,4 @@ obj-y += faraday_a369.o \ obj-y += ftintc020.o obj-y += ftahbc020.o obj-y += ftddrii030.o +obj-y += ftpwmtmr010.o diff --git a/hw/arm/faraday_a369_soc.c b/hw/arm/faraday_a369_soc.c index 1021405..d4b2677 100644 --- a/hw/arm/faraday_a369_soc.c +++ b/hw/arm/faraday_a369_soc.c @@ -151,6 +151,16 @@ a369soc_device_init(FaradaySoCState *s) /* ftddrii030 */ s->ddrc = sysbus_create_simple("ftddrii030", 0x93100000, NULL); + + /* Timer */ + ds = qdev_create(NULL, "ftpwmtmr010"); + qdev_prop_set_uint32(ds, "freq", 66 * 1000000); + qdev_init_nofail(ds); + sysbus_mmio_map(SYS_BUS_DEVICE(ds), 0, 0x92300000); + sysbus_connect_irq(SYS_BUS_DEVICE(ds), 0, pic[8]); + sysbus_connect_irq(SYS_BUS_DEVICE(ds), 1, pic[9]); + sysbus_connect_irq(SYS_BUS_DEVICE(ds), 2, pic[10]); + sysbus_connect_irq(SYS_BUS_DEVICE(ds), 3, pic[11]); } static int a369soc_init(SysBusDevice *busdev) diff --git a/hw/arm/ftpwmtmr010.c b/hw/arm/ftpwmtmr010.c new file mode 100644 index 0000000..fcca381 --- /dev/null +++ b/hw/arm/ftpwmtmr010.c @@ -0,0 +1,257 @@ +/* + * Faraday FTPWMTMR010 Timer. + * + * Copyright (c) 2012 Faraday Technology + * Written by Dante Su + * + * This code is licensed under GNU GPL v2+. + */ + +#include "hw/hw.h" +#include "hw/sysbus.h" +#include "qemu/timer.h" +#include "sysemu/sysemu.h" + +#include "faraday.h" +#include "ftpwmtmr010.h" + +#define TYPE_FTPWMTMR010 "ftpwmtmr010" +#define TYPE_FTPWMTMR010_TIMER "ftpwmtmr010_timer" + +typedef struct Ftpwmtmr010State Ftpwmtmr010State; + +typedef struct Ftpwmtmr010Timer { + uint32_t ctrl; + uint32_t cntb; + int id; + uint64_t timeout; + uint64_t countdown; + qemu_irq irq; + QEMUTimer *qtimer; + Ftpwmtmr010State *chip; +} Ftpwmtmr010Timer; + +struct Ftpwmtmr010State { + SysBusDevice busdev; + + MemoryRegion iomem; + Ftpwmtmr010Timer timer[8]; + uint32_t freq; /* desired source clock */ + uint64_t step; /* get_ticks_per_sec() / freq */ + uint32_t stat; +}; + +#define FTPWMTMR010(obj) \ + OBJECT_CHECK(Ftpwmtmr010State, obj, TYPE_FTPWMTMR010) + +static uint64_t +ftpwmtmr010_mem_read(void *opaque, hwaddr addr, unsigned size) +{ + Ftpwmtmr010State *s = FTPWMTMR010(opaque); + Ftpwmtmr010Timer *t; + uint64_t now = qemu_get_clock_ns(vm_clock); + uint64_t ret = 0; + + switch (addr) { + case REG_SR: + ret = s->stat; + break; + case REG_REVR: + ret = 0x00000000; /* Rev. 0.0.0 (no rev. id) */ + break; + case REG_TIMER_BASE(1) ... REG_TIMER_BASE(8) + 0x0C: + t = s->timer + (addr >> 4) - 1; + switch (addr & 0x0f) { + case REG_TIMER_CTRL: + return t->ctrl; + case REG_TIMER_CNTB: + return t->cntb; + case REG_TIMER_CNTO: + if ((t->ctrl & TIMER_CTRL_START) && (t->timeout > now)) { + ret = (t->timeout - now) / s->step; + } + break; + } + break; + default: + break; + } + + return ret; +} + +static void +ftpwmtmr010_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + Ftpwmtmr010State *s = FTPWMTMR010(opaque); + Ftpwmtmr010Timer *t; + int i; + + switch (addr) { + case REG_SR: + s->stat &= ~((uint32_t)val); + for (i = 0; i < 8; ++i) { + if (val & BIT(i)) { + qemu_irq_lower(s->timer[i].irq); + } + } + break; + case REG_TIMER_BASE(1) ... REG_TIMER_BASE(8) + 0x0C: + t = s->timer + (addr >> 4) - 1; + switch (addr & 0x0f) { + case REG_TIMER_CTRL: + t->ctrl = (uint32_t)val; + if (t->ctrl & TIMER_CTRL_UPDATE) { + t->countdown = (uint64_t)t->cntb * s->step; + } + if (t->ctrl & TIMER_CTRL_START) { + t->timeout = t->countdown + qemu_get_clock_ns(vm_clock); + qemu_mod_timer(t->qtimer, t->timeout); + } + break; + case REG_TIMER_CNTB: + t->cntb = (uint32_t)val; + break; + } + break; + default: + break; + } +} + +static const MemoryRegionOps ftpwmtmr010_ops = { + .read = ftpwmtmr010_mem_read, + .write = ftpwmtmr010_mem_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + +static void ftpwmtmr010_timer_tick(void *opaque) +{ + Ftpwmtmr010Timer *t = opaque; + Ftpwmtmr010State *s = t->chip; + + /* if the timer has been enabled/started */ + if (!(t->ctrl & TIMER_CTRL_START)) { + return; + } + + /* if the interrupt enabled */ + if (t->ctrl & TIMER_CTRL_INTR) { + s->stat |= BIT(t->id); + if (t->ctrl & TIMER_CTRL_INTR_EDGE) { + qemu_irq_pulse(t->irq); + } else { + qemu_irq_raise(t->irq); + } + } + + /* if auto-reload is enabled */ + if (t->ctrl & TIMER_CTRL_AUTORELOAD) { + t->timeout = t->countdown + qemu_get_clock_ns(vm_clock); + qemu_mod_timer(t->qtimer, t->timeout); + } else { + t->ctrl &= ~TIMER_CTRL_START; + } +} + +static void ftpwmtmr010_reset(DeviceState *ds) +{ + SysBusDevice *busdev = SYS_BUS_DEVICE(ds); + Ftpwmtmr010State *s = FTPWMTMR010(FROM_SYSBUS(Ftpwmtmr010State, busdev)); + int i; + + s->stat = 0; + + for (i = 0; i < 8; ++i) { + s->timer[i].ctrl = 0; + s->timer[i].cntb = 0; + s->timer[i].timeout = 0; + qemu_irq_lower(s->timer[i].irq); + qemu_del_timer(s->timer[i].qtimer); + } +} + +static int ftpwmtmr010_init(SysBusDevice *busdev) +{ + Ftpwmtmr010State *s = FTPWMTMR010(FROM_SYSBUS(Ftpwmtmr010State, busdev)); + int i; + + s->step = (uint64_t)get_ticks_per_sec() / (uint64_t)s->freq; + + DPRINTF("ftpwmtmr010 freq=%d\n", s->freq); + + memory_region_init_io(&s->iomem, + &ftpwmtmr010_ops, + s, + TYPE_FTPWMTMR010, + 0x1000); + sysbus_init_mmio(busdev, &s->iomem); + for (i = 0; i < 8; ++i) { + s->timer[i].id = i; + s->timer[i].chip = s; + s->timer[i].qtimer = qemu_new_timer_ns(vm_clock, + ftpwmtmr010_timer_tick, + &s->timer[i]); + sysbus_init_irq(busdev, &s->timer[i].irq); + } + + return 0; +} + +static const VMStateDescription vmstate_ftpwmtmr010_timer = { + .name = TYPE_FTPWMTMR010_TIMER, + .version_id = 2, + .minimum_version_id = 2, + .minimum_version_id_old = 2, + .fields = (VMStateField[]) { + VMSTATE_UINT32(ctrl, Ftpwmtmr010Timer), + VMSTATE_UINT32(cntb, Ftpwmtmr010Timer), + VMSTATE_END_OF_LIST(), + }, +}; + +static const VMStateDescription vmstate_ftpwmtmr010 = { + .name = TYPE_FTPWMTMR010, + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(stat, Ftpwmtmr010State), + VMSTATE_UINT32(freq, Ftpwmtmr010State), + VMSTATE_UINT64(step, Ftpwmtmr010State), + VMSTATE_STRUCT_ARRAY(timer, Ftpwmtmr010State, 8, 1, + vmstate_ftpwmtmr010_timer, Ftpwmtmr010Timer), + VMSTATE_END_OF_LIST(), + } +}; + +static Property ftpwmtmr010_properties[] = { + DEFINE_PROP_UINT32("freq", Ftpwmtmr010State, freq, 66000000), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ftpwmtmr010_class_init(ObjectClass *klass, void *data) +{ + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + k->init = ftpwmtmr010_init; + dc->vmsd = &vmstate_ftpwmtmr010; + dc->props = ftpwmtmr010_properties; + dc->reset = ftpwmtmr010_reset; + dc->no_user = 1; +} + +static const TypeInfo ftpwmtmr010_info = { + .name = TYPE_FTPWMTMR010, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Ftpwmtmr010State), + .class_init = ftpwmtmr010_class_init, +}; + +static void ftpwmtmr010_register_types(void) +{ + type_register_static(&ftpwmtmr010_info); +} + +type_init(ftpwmtmr010_register_types) diff --git a/hw/arm/ftpwmtmr010.h b/hw/arm/ftpwmtmr010.h new file mode 100644 index 0000000..eeaf48a --- /dev/null +++ b/hw/arm/ftpwmtmr010.h @@ -0,0 +1,29 @@ +/* + * Faraday FTPWMTMR010 Timer. + * + * Copyright (c) 2012 Faraday Technology + * Written by Dante Su + * + * This code is licensed under GNU GPL v2+. + */ + +#ifndef HW_ARM_FTPWMTMR010_H +#define HW_ARM_FTPWMTMR010_H + +#define REG_SR 0x00 /* status register */ +#define REG_REVR 0x90 /* revision register */ + +#define REG_TIMER_BASE(id) (0x00 + ((id) << 4)) +#define REG_TIMER_CTRL 0x00 +#define REG_TIMER_CNTB 0x04 +#define REG_TIMER_CMPB 0x08 +#define REG_TIMER_CNTO 0x0C + +#define TIMER_CTRL_EXTCK BIT(0) /* external clock */ +#define TIMER_CTRL_START BIT(1) +#define TIMER_CTRL_UPDATE BIT(2) +#define TIMER_CTRL_AUTORELOAD BIT(4) +#define TIMER_CTRL_INTR BIT(5) /* interrupt enabled */ +#define TIMER_CTRL_INTR_EDGE BIT(6) /* interrupt type: 1=edge 0=level */ + +#endif