Message ID | 1361870382-743-8-git-send-email-tiejun.chen@windriver.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Benjamin Herrenschmidt |
Headers | show |
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 038e81d..e60f078 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -129,6 +129,10 @@ __secondary_hold: /* Grab our physical cpu number */ mr r24,r3 /* stash r4 for book3e */ +#ifdef CONFIG_PPC_FSL_BOOK3E + /* we need to setup initial TLB entry. */ + li r4,0 +#endif mr r25,r4 /* Tell the master cpu we're here */
In commit 96f013f, "powerpc/kexec: Add kexec "hold" support for Book3e processors", requires that GPR4 survive the "hold" process, for IBM Blue Gene/Q with with some very strange firmware. But for FSL Book3E, r4 = 1 to indicate that the initial TLB entry for this core already exists so we still should set r4 with 0 to create that initial TLB. Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com> --- arch/powerpc/kernel/head_64.S | 4 ++++ 1 file changed, 4 insertions(+)