From patchwork Tue Feb 26 08:05:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aneesh Kumar K.V" X-Patchwork-Id: 223127 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id E16502C0C2C for ; Tue, 26 Feb 2013 19:11:14 +1100 (EST) Received: from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "e23smtp03.au.ibm.com", Issuer "GeoTrust SSL CA" (not verified)) by ozlabs.org (Postfix) with ESMTPS id EC42B2C0379 for ; Tue, 26 Feb 2013 19:05:50 +1100 (EST) Received: from /spool/local by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 26 Feb 2013 17:59:38 +1000 Received: from d23relay04.au.ibm.com (d23relay04.au.ibm.com [9.190.234.120]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 83AEE357804A for ; Tue, 26 Feb 2013 19:05:47 +1100 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay04.au.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r1Q7rKVO12124584 for ; Tue, 26 Feb 2013 18:53:20 +1100 Received: from d23av03.au.ibm.com (loopback [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r1Q85krw007987 for ; Tue, 26 Feb 2013 19:05:46 +1100 Received: from skywalker.in.ibm.com (skywalker.in.ibm.com [9.124.35.167]) by d23av03.au.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id r1Q85NvQ007256; Tue, 26 Feb 2013 19:05:44 +1100 From: "Aneesh Kumar K.V" To: benh@kernel.crashing.org, paulus@samba.org Subject: [PATCH -V1 11/24] powerpc: Update tlbie/tlbiel as per ISA doc Date: Tue, 26 Feb 2013 13:35:01 +0530 Message-Id: <1361865914-13911-12-git-send-email-aneesh.kumar@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1361865914-13911-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> References: <1361865914-13911-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13022607-6102-0000-0000-0000030FC566 Cc: linux-mm@kvack.org, linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: "Aneesh Kumar K.V" This make sure we handle multiple page size segment correctly. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/mm/hash_native_64.c | 52 +++++++++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c index e2d816d..e800b26 100644 --- a/arch/powerpc/mm/hash_native_64.c +++ b/arch/powerpc/mm/hash_native_64.c @@ -39,7 +39,7 @@ DEFINE_RAW_SPINLOCK(native_tlbie_lock); -static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize) +static inline void __tlbie(unsigned long vpn, int bpsize, int apsize, int ssize) { unsigned long va; unsigned int penc; @@ -59,19 +59,33 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize) */ va &= ~(0xffffULL << 48); - switch (psize) { + switch (bpsize) { case MMU_PAGE_4K: + /* clear out bits after (52) [0....52.....63] */ + va &= ~((1ul << (64 - 52)) - 1); va |= ssize << 8; + va |= mmu_psize_defs[apsize].sllp << 6; asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2) : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) : "memory"); break; default: /* We need 14 to 14 + i bits of va */ - penc = mmu_psize_defs[psize].penc[apsize]; - va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); + penc = mmu_psize_defs[bpsize].penc[apsize]; + /* clear out bits after (44) [0....44.....63] */ + va &= ~((1ul << (64 - 44)) - 1); va |= penc << 12; va |= ssize << 8; + /* Add AVAL part */ + if (bpsize != apsize) { + /* + * MPSS, 64K base page size and 16MB parge page size + * We don't need all the bits, but this seems to work. + * vpn cover upto 65 bits of va. (0...65) and we need + * 56..62 bits of va. + */ + va |= ((vpn >> 2) & 0xfe); + } va |= 1; /* L */ asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2) : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) @@ -80,7 +94,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize) } } -static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize) +static inline void __tlbiel(unsigned long vpn, int bpsize, int apsize, int ssize) { unsigned long va; unsigned int penc; @@ -94,18 +108,32 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize) */ va &= ~(0xffffULL << 48); - switch (psize) { + switch (bpsize) { case MMU_PAGE_4K: + /* clear out bits after(52) [0....52.....63] */ + va &= ~((1ul << (64 - 52)) - 1); va |= ssize << 8; + va |= mmu_psize_defs[apsize].sllp << 6; asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)" : : "r"(va) : "memory"); break; default: /* We need 14 to 14 + i bits of va */ - penc = mmu_psize_defs[psize].penc[apsize]; - va &= ~((1ul << mmu_psize_defs[psize].shift) - 1); + penc = mmu_psize_defs[bpsize].penc[apsize]; + /* clear out bits after(44) [0....44.....63] */ + va &= ~((1ul << (64 - 44)) - 1); va |= penc << 12; va |= ssize << 8; + /* Add AVAL part */ + if (bpsize != apsize) { + /* + * MPSS, 64K base page size and 16MB parge page size + * We don't need all the bits, but this seems to work. + * vpn cover upto 65 bits of va. (0...65) and we need + * 56..62 bits of va. + */ + va |= ((vpn >> 2) & 0xfe); + } va |= 1; /* L */ asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)" : : "r"(va) : "memory"); @@ -114,22 +142,22 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize) } -static inline void tlbie(unsigned long vpn, int psize, int apsize, +static inline void tlbie(unsigned long vpn, int bpsize, int apsize, int ssize, int local) { unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL); int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE); if (use_local) - use_local = mmu_psize_defs[psize].tlbiel; + use_local = mmu_psize_defs[bpsize].tlbiel; if (lock_tlbie && !use_local) raw_spin_lock(&native_tlbie_lock); asm volatile("ptesync": : :"memory"); if (use_local) { - __tlbiel(vpn, psize, apsize, ssize); + __tlbiel(vpn, bpsize, apsize, ssize); asm volatile("ptesync": : :"memory"); } else { - __tlbie(vpn, psize, apsize, ssize); + __tlbie(vpn, bpsize, apsize, ssize); asm volatile("eieio; tlbsync; ptesync": : :"memory"); } if (lock_tlbie && !use_local)