From patchwork Mon Feb 25 20:16:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 223031 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 38D5E2C008E for ; Tue, 26 Feb 2013 07:17:40 +1100 (EST) Received: from localhost ([::1]:44356 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA4UU-0005dJ-9i for incoming@patchwork.ozlabs.org; Mon, 25 Feb 2013 15:17:38 -0500 Received: from eggs.gnu.org ([208.118.235.92]:46749) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA4Tf-0003kB-Rd for qemu-devel@nongnu.org; Mon, 25 Feb 2013 15:16:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UA4Ta-0004MF-Rx for qemu-devel@nongnu.org; Mon, 25 Feb 2013 15:16:47 -0500 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:60716 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA4Ta-0004M8-Kj for qemu-devel@nongnu.org; Mon, 25 Feb 2013 15:16:42 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1UA4TN-000725-OC; Mon, 25 Feb 2013 20:16:29 +0000 From: Peter Maydell To: Anthony Liguori , Aurelien Jarno , Blue Swirl Date: Mon, 25 Feb 2013 20:16:29 +0000 Message-Id: <1361823389-27006-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1361823389-27006-1-git-send-email-peter.maydell@linaro.org> References: <1361823389-27006-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: qemu-devel@nongnu.org, Paul Brook Subject: [Qemu-devel] [PATCH 2/2] target-arm: Fix sbc_CC carry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Richard Henderson While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits, it does not produce the correct carry-out to bit 33. Do exactly what the manual says. Using the ~T1 makes the add and subtract code paths nearly identical, so have sbc_CC use adc_CC. Cc: Peter Maydell Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- target-arm/translate.c | 28 ++++------------------------ 1 file changed, 4 insertions(+), 24 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 6d91b70..f2f649d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -464,33 +464,13 @@ static void gen_sub_CC(TCGv dest, TCGv t0, TCGv t1) tcg_gen_mov_i32(dest, cpu_NF); } -/* dest = T0 + ~T1 + CF = T0 - T1 + CF - 1. Compute C, N, V and Z flags */ +/* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */ static void gen_sbc_CC(TCGv dest, TCGv t0, TCGv t1) { TCGv tmp = tcg_temp_new_i32(); - tcg_gen_subi_i32(cpu_CF, cpu_CF, 1); - if (TCG_TARGET_HAS_add2_i32) { - tcg_gen_movi_i32(tmp, 0); - tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp); - tcg_gen_sub2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp); - } else { - TCGv_i64 q0 = tcg_temp_new_i64(); - TCGv_i64 q1 = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(q0, t0); - tcg_gen_extu_i32_i64(q1, t1); - tcg_gen_sub_i64(q0, q0, q1); - tcg_gen_extu_i32_i64(q1, cpu_CF); - tcg_gen_add_i64(q0, q0, q1); - tcg_gen_extr_i64_i32(cpu_NF, cpu_CF, q0); - tcg_temp_free_i64(q0); - tcg_temp_free_i64(q1); - } - tcg_gen_mov_i32(cpu_ZF, cpu_NF); - tcg_gen_xor_i32(cpu_VF, cpu_NF, t0); - tcg_gen_xor_i32(tmp, t0, t1); - tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); - tcg_temp_free_i32(tmp); - tcg_gen_mov_i32(dest, cpu_NF); + tcg_gen_not_i32(tmp, t1); + gen_adc_CC(dest, t0, tmp); + tcg_temp_free(tmp); } #define GEN_SHIFT(name) \