From patchwork Mon Feb 25 20:16:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 223029 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A80912C007E for ; Tue, 26 Feb 2013 07:16:56 +1100 (EST) Received: from localhost ([::1]:40844 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA4Tl-0003kQ-M1 for incoming@patchwork.ozlabs.org; Mon, 25 Feb 2013 15:16:53 -0500 Received: from eggs.gnu.org ([208.118.235.92]:46678) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA4TY-0003j2-Sg for qemu-devel@nongnu.org; Mon, 25 Feb 2013 15:16:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UA4TT-0004KH-Lh for qemu-devel@nongnu.org; Mon, 25 Feb 2013 15:16:40 -0500 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:60710 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA4TT-0004Jx-BO for qemu-devel@nongnu.org; Mon, 25 Feb 2013 15:16:35 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1UA4TN-000723-Mw; Mon, 25 Feb 2013 20:16:29 +0000 From: Peter Maydell To: Anthony Liguori , Aurelien Jarno , Blue Swirl Date: Mon, 25 Feb 2013 20:16:28 +0000 Message-Id: <1361823389-27006-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1361823389-27006-1-git-send-email-peter.maydell@linaro.org> References: <1361823389-27006-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Cc: qemu-devel@nongnu.org, Paul Brook Subject: [Qemu-devel] [PATCH 1/2] arm/translate.c: Fix adc_CC/sbc_CC implementation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite commits 49b4c31efcce45ab714f286f14fa5d5173f9069d and 2de68a4900ef6eb67380b0c128abfe1976bc66e8 reworked the implementation of adc_CC and sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path) are incorrect. The new logic is: CF:NF = 0:A +/- 0:CF CF:NF = CF:A +/- 0:B The lower 32 bits of the intermediate result stored in NF needs to be passes into the second addition in place of A (s/CF:A/CF:NF): CF:NF = 0:A +/- 0:CF CF:NF = CF:NF +/- 0:B This patch fixes the issue. Cc: Peter Maydell Signed-off-by: Peter Crosthwaite Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- target-arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 9993aea..6d91b70 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -428,7 +428,7 @@ static void gen_adc_CC(TCGv dest, TCGv t0, TCGv t1) if (TCG_TARGET_HAS_add2_i32) { tcg_gen_movi_i32(tmp, 0); tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp); - tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, cpu_CF, t1, tmp); + tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp); } else { TCGv_i64 q0 = tcg_temp_new_i64(); TCGv_i64 q1 = tcg_temp_new_i64(); @@ -472,7 +472,7 @@ static void gen_sbc_CC(TCGv dest, TCGv t0, TCGv t1) if (TCG_TARGET_HAS_add2_i32) { tcg_gen_movi_i32(tmp, 0); tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp); - tcg_gen_sub2_i32(cpu_NF, cpu_CF, t0, cpu_CF, t1, tmp); + tcg_gen_sub2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp); } else { TCGv_i64 q0 = tcg_temp_new_i64(); TCGv_i64 q1 = tcg_temp_new_i64();