From patchwork Mon Feb 25 19:01:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 223022 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2B9522C00DC for ; Tue, 26 Feb 2013 06:22:23 +1100 (EST) Received: from localhost ([::1]:45805 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA3K0-0004H0-Mk for incoming@patchwork.ozlabs.org; Mon, 25 Feb 2013 14:02:44 -0500 Received: from eggs.gnu.org ([208.118.235.92]:37998) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA3JI-0003Eb-Tv for qemu-devel@nongnu.org; Mon, 25 Feb 2013 14:02:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UA3JC-0004Wv-4g for qemu-devel@nongnu.org; Mon, 25 Feb 2013 14:02:00 -0500 Received: from mail-qe0-f50.google.com ([209.85.128.50]:34531) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA3JB-0004Wr-V9 for qemu-devel@nongnu.org; Mon, 25 Feb 2013 14:01:53 -0500 Received: by mail-qe0-f50.google.com with SMTP id w7so1802565qeb.37 for ; Mon, 25 Feb 2013 11:01:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=6orwHTdCPZb81dw4K1uJ0tmeYoOjux9pL9rlw+CzC4I=; b=yrsLdxJhAXfvjIlnuvUCtoIvWY4jh/rOXcFhd59VzfuXPzzUhguBsVrRZEfh1u0w8P TOg/cjOrhR43WbZbCZhOG7PVzC7Tvm8MuePYP6ZvjvuCJvya3kKihAxQXmlH6y4oPlTT Vr06c87bpaqKp0A3OWVwCAATp/jU1h7+M50HA+kALbQ8toV0sDlfv5T1QVmxMeMk1v8e SByVaB+nwZkyGv75HKEocEPWfFCH19rQqLjPIHyGVHa1FKOk42eQJ/4MPGAiB/ds84zN axr31XwlQLG0Nq28ynFApgygA6d3PgKh4yYcTg4kFbssqT/+2z3+BqFrrYEsC2vF5NIo pbTA== X-Received: by 10.224.10.141 with SMTP id p13mr12995208qap.40.1361818913426; Mon, 25 Feb 2013 11:01:53 -0800 (PST) Received: from anchor.com (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id gw9sm17992087qab.10.2013.02.25.11.01.51 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 25 Feb 2013 11:01:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 25 Feb 2013 11:01:15 -0800 Message-Id: <1361818877-8739-2-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1361818877-8739-1-git-send-email-rth@twiddle.net> References: <1361818877-8739-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.128.50 Cc: Peter Maydell , Anthony Liguori , Peter Crosthwaite Subject: [Qemu-devel] [PATCH v2 1/3] arm/translate.c: Fix adc_CC/sbc_CC implementation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite commits 49b4c31efcce45ab714f286f14fa5d5173f9069d and 2de68a4900ef6eb67380b0c128abfe1976bc66e8 reworked the implementation of adc_CC and sub_CC. The new implementations (on the TCG_TARGET_HAS_add2_i32 code path) are incorrect. The new logic is: CF:NF = 0:A +/- 0:CF CF:NF = CF:A +/- 0:B The lower 32 bits of the intermediate result stored in NF needs to be passes into the second addition in place of A (s/CF:A/CF:NF): CF:NF = 0:A +/- 0:CF CF:NF = CF:NF +/- 0:B This patch fixes the issue. Cc: Peter Maydell Signed-off-by: Peter Crosthwaite Signed-off-by: Richard Henderson --- target-arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 9993aea..6d91b70 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -428,7 +428,7 @@ static void gen_adc_CC(TCGv dest, TCGv t0, TCGv t1) if (TCG_TARGET_HAS_add2_i32) { tcg_gen_movi_i32(tmp, 0); tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp); - tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, cpu_CF, t1, tmp); + tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp); } else { TCGv_i64 q0 = tcg_temp_new_i64(); TCGv_i64 q1 = tcg_temp_new_i64(); @@ -472,7 +472,7 @@ static void gen_sbc_CC(TCGv dest, TCGv t0, TCGv t1) if (TCG_TARGET_HAS_add2_i32) { tcg_gen_movi_i32(tmp, 0); tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp); - tcg_gen_sub2_i32(cpu_NF, cpu_CF, t0, cpu_CF, t1, tmp); + tcg_gen_sub2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp); } else { TCGv_i64 q0 = tcg_temp_new_i64(); TCGv_i64 q1 = tcg_temp_new_i64();