From patchwork Mon Feb 25 19:01:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [v2,2/3] target-arm: Fix sbc_CC carry Date: Mon, 25 Feb 2013 09:01:16 -0000 From: Richard Henderson X-Patchwork-Id: 223013 Message-Id: <1361818877-8739-3-git-send-email-rth@twiddle.net> To: qemu-devel@nongnu.org Cc: Peter Maydell , Anthony Liguori While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits, it does not produce the correct carry-out to bit 33. Do exactly what the manual says. Cc: Peter Maydell Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target-arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 6d91b70..eade159 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -464,20 +464,20 @@ static void gen_sub_CC(TCGv dest, TCGv t0, TCGv t1) tcg_gen_mov_i32(dest, cpu_NF); } -/* dest = T0 + ~T1 + CF = T0 - T1 + CF - 1. Compute C, N, V and Z flags */ +/* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */ static void gen_sbc_CC(TCGv dest, TCGv t0, TCGv t1) { TCGv tmp = tcg_temp_new_i32(); - tcg_gen_subi_i32(cpu_CF, cpu_CF, 1); + tcg_gen_not_i32(cpu_ZF, t1); if (TCG_TARGET_HAS_add2_i32) { tcg_gen_movi_i32(tmp, 0); tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp); - tcg_gen_sub2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp); + tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, cpu_ZF, tmp); } else { TCGv_i64 q0 = tcg_temp_new_i64(); TCGv_i64 q1 = tcg_temp_new_i64(); tcg_gen_extu_i32_i64(q0, t0); - tcg_gen_extu_i32_i64(q1, t1); + tcg_gen_extu_i32_i64(q1, cpu_ZF); tcg_gen_sub_i64(q0, q0, q1); tcg_gen_extu_i32_i64(q1, cpu_CF); tcg_gen_add_i64(q0, q0, q1);