From patchwork Mon Feb 25 18:30:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 223003 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BDED22C0092 for ; Tue, 26 Feb 2013 05:31:34 +1100 (EST) Received: from localhost ([::1]:42910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA2po-00011w-S0 for incoming@patchwork.ozlabs.org; Mon, 25 Feb 2013 13:31:32 -0500 Received: from eggs.gnu.org ([208.118.235.92]:50842) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA2pS-0000mL-NQ for qemu-devel@nongnu.org; Mon, 25 Feb 2013 13:31:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UA2pL-00031k-86 for qemu-devel@nongnu.org; Mon, 25 Feb 2013 13:31:10 -0500 Received: from mail-qa0-f49.google.com ([209.85.216.49]:39430) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UA2pL-00031b-29 for qemu-devel@nongnu.org; Mon, 25 Feb 2013 13:31:03 -0500 Received: by mail-qa0-f49.google.com with SMTP id o13so1754516qaj.15 for ; Mon, 25 Feb 2013 10:31:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=vAjV/R4cdtfIgJYmi/fkFG7HtQvsGjvfHRMU67FIiV0=; b=0LlRsDEC0nF9I+/ZlCUP1rF5dMRzM+rcgJfCxyhj+a8WJtOLUtElpTPzDCirCAEMTp nKms5FYIOtCVJAJvmlyt4OqNH8DJDhjYbL6IJS1hbfmxJPGctwCQyErLh4wRsXpyBodm E02upaF4nDIx5WCIqxpYdfcjrZ1nN+uN1kZiBEZkRs/rkeZnrD7bVlOdbRii/73Toi+G geJZB15z7PHAabeHqKoC8NJ0Ih57bqkd+IoYY59d641UE8mkHWZPsZQhCXFe2QEMafUL WpYL84JN/r5GkOLVeyWVwvG5ZGwOH6mBjLX5esVei+4py5aExPAh/vEBT3niWvtzHmkq xlYw== X-Received: by 10.224.31.16 with SMTP id w16mr12473717qac.52.1361817062521; Mon, 25 Feb 2013 10:31:02 -0800 (PST) Received: from anchor.com (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id x9sm17329664qen.1.2013.02.25.10.31.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 25 Feb 2013 10:31:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 25 Feb 2013 10:30:22 -0800 Message-Id: <1361817023-4842-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1361817023-4842-1-git-send-email-rth@twiddle.net> References: <1361817023-4842-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.216.49 Cc: Peter Maydell , Anthony Liguori Subject: [Qemu-devel] [PATCH 2/3] target-arm: Fix sbc_CC carry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org While T0+~T1+CF = T0-T1+CF-1 is true for the low 32-bits, it does not produce the correct carry-out to bit 33. Do exactly what the manual says. Cc: Peter Maydell Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- target-arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 6d91b70..a2ce29f 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -464,20 +464,20 @@ static void gen_sub_CC(TCGv dest, TCGv t0, TCGv t1) tcg_gen_mov_i32(dest, cpu_NF); } -/* dest = T0 + ~T1 + CF = T0 - T1 + CF - 1. Compute C, N, V and Z flags */ +/* dest = T0 + ~T1 + CF. Compute C, N, V and Z flags */ static void gen_sbc_CC(TCGv dest, TCGv t0, TCGv t1) { TCGv tmp = tcg_temp_new_i32(); - tcg_gen_subi_i32(cpu_CF, cpu_CF, 1); + tcg_gen_not_i32(cpu_ZF, t1); if (TCG_TARGET_HAS_add2_i32) { tcg_gen_movi_i32(tmp, 0); tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp); - tcg_gen_sub2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp); + tcg_gen_sub2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, cpu_ZF, tmp); } else { TCGv_i64 q0 = tcg_temp_new_i64(); TCGv_i64 q1 = tcg_temp_new_i64(); tcg_gen_extu_i32_i64(q0, t0); - tcg_gen_extu_i32_i64(q1, t1); + tcg_gen_extu_i32_i64(q1, cpu_ZF); tcg_gen_sub_i64(q0, q0, q1); tcg_gen_extu_i32_i64(q1, cpu_CF); tcg_gen_add_i64(q0, q0, q1);