Patchwork [v2,8/8] xilinx_axienet: stub out second stream connection

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Submitter Peter Crosthwaite
Date Feb. 25, 2013, 8:50 a.m.
Message ID <9f6319cf1501490d9ab819b7780c7ffbe8157227.1361782087.git.peter.crosthwaite@xilinx.com>
Download mbox | patch
Permalink /patch/222866/
State New
Headers show

Comments

Peter Crosthwaite - Feb. 25, 2013, 8:50 a.m.
Example patch adding a second proxy object for the second stream connection of
axienet.

This is a non-functional RFC, please see the cover letter for discussion.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---
changed from v1:
Rebased on series refactorings

 hw/xilinx_axienet.c |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

Patch

diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
index a4ec1d8..e5a99e8 100644
--- a/hw/xilinx_axienet.c
+++ b/hw/xilinx_axienet.c
@@ -33,6 +33,7 @@ 
 
 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
 #define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
+#define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream"
 
 #define XILINX_AXI_ENET(obj) \
      OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
@@ -41,6 +42,10 @@ 
      OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
      TYPE_XILINX_AXI_ENET_DATA_STREAM)
 
+#define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
+     OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
+     TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
+
 /* Advertisement control register. */
 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
@@ -330,6 +335,7 @@  struct XilinxAXIEnet {
     qemu_irq irq;
     StreamSlave *tx_dev;
     XilinxAXIEnetStreamSlave rx_data_dev;
+    XilinxAXIEnetStreamSlave rx_control_dev;
     NICState *nic;
     NICConf conf;
 
@@ -813,6 +819,13 @@  static void eth_cleanup(NetClientState *nc)
 }
 
 static void
+axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,
+                            uint32_t *hdr)
+{
+    /* ... */
+}
+
+static void
 axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,
                          uint32_t *hdr)
 {
@@ -869,14 +882,19 @@  static void xilinx_enet_realize(DeviceState *dev, Error **errp)
 {
     XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
     XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
+    XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
+                                                            &s->rx_control_dev);
     Error *local_errp = NULL;
 
     object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
                              (Object **) &ds->enet, &local_errp);
+    object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet",
+                             (Object **) &ds->enet, &local_errp);
     if (local_errp) {
         goto xilinx_enet_realize_fail;
     }
     object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_errp);
+    object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_errp);
     if (local_errp) {
         goto xilinx_enet_realize_fail;
     }
@@ -911,9 +929,13 @@  static void xilinx_enet_init(Object *obj)
     assert_no_error(errp);
 
     object_initialize(&s->rx_data_dev, TYPE_XILINX_AXI_ENET_DATA_STREAM);
+    object_initialize(&s->rx_control_dev, TYPE_XILINX_AXI_ENET_CONTROL_STREAM);
     object_property_add_child(OBJECT(s), "axistream-connected-target",
                               (Object *)&s->rx_data_dev, &errp);
     assert_no_error(errp);
+    object_property_add_child(OBJECT(s), "axistream-control-connected-target",
+                              (Object *)&s->rx_control_dev, &errp);
+    assert_no_error(errp);
 
     sysbus_init_irq(sbd, &s->irq);
 
@@ -965,10 +987,23 @@  static const TypeInfo xilinx_enet_data_stream_info = {
     }
 };
 
+static const TypeInfo xilinx_enet_control_stream_info = {
+    .name          = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
+    .parent        = TYPE_OBJECT,
+    .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
+    .class_init    = xilinx_enet_stream_class_init,
+    .class_data    = axienet_control_stream_push,
+    .interfaces = (InterfaceInfo[]) {
+            { TYPE_STREAM_SLAVE },
+            { }
+    }
+};
+
 static void xilinx_enet_register_types(void)
 {
     type_register_static(&xilinx_enet_info);
     type_register_static(&xilinx_enet_data_stream_info);
+    type_register_static(&xilinx_enet_control_stream_info);
 }
 
 type_init(xilinx_enet_register_types)