From patchwork Thu Feb 21 20:49:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aaron Sierra X-Patchwork-Id: 222412 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8BBBD2C02A1 for ; Fri, 22 Feb 2013 07:50:27 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U8d54-0002vs-EA; Thu, 21 Feb 2013 20:49:26 +0000 Received: from xes-mad.com ([216.165.139.218]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U8d4w-0002um-Uk for linux-mtd@lists.infradead.org; Thu, 21 Feb 2013 20:49:19 +0000 Received: from zimbra.xes-mad.com (cal [10.52.0.127]) by xes-mad.com (8.13.8/8.13.8) with ESMTP id r1LKn7Sr030224; Thu, 21 Feb 2013 14:49:07 -0600 Date: Thu, 21 Feb 2013 14:49:07 -0600 (CST) From: Aaron Sierra To: Kumar Gala Subject: [PATCH 1/3] powerpc/fsl_lbc: Synchronize MAR/MxMR writes Message-ID: In-Reply-To: MIME-Version: 1.0 X-Originating-IP: [10.52.0.65] X-Mailer: Zimbra 7.1.3_GA_3346 (ZimbraWebClient - GC24 (Linux)/7.1.3_GA_3346) X-Virus-Scanned: clamav-milter 0.96 at mail X-Virus-Status: Clean X-Spam-Status: No, score=-5.9 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00 autolearn=no version=3.2.5 X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on mail.xes-mad.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130221_154919_155523_57786D2F X-CRM114-Status: UNSURE ( 9.84 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Artem Bityutskiy , linux-mtd@lists.infradead.org, Nate Case , David Woodhouse X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Author: Nate Case According to Freescale documentation, it is necessary to perform a dummy read after writing to the MxMR/MDR registers. This dummy read will ensure that the write took effect before performing the subsequent write to the UPM region. Although the documentation does not mention the MAR register (only MxMR and MDR), it has been shown on a P4080 platform that UPM cycles would on rare occurrence utilize a stale value for MAR from the previous pattern. Inserting a dummy read after writing MAR corrects this problem. This fixes a problem observed using a UPM NAND flash device where NAND commands would occasionally get corrupted. Signed-off-by: Nate Case --- arch/powerpc/include/asm/fsl_lbc.h | 1 + arch/powerpc/sysdev/fsl_lbc.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 420b453..19e0cd2 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -263,6 +263,7 @@ extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm); static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset) { clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset); + (void) in_be32(upm->mxmr); } /** diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c index 6bc5a54..9b4f0cf 100644 --- a/arch/powerpc/sysdev/fsl_lbc.c +++ b/arch/powerpc/sysdev/fsl_lbc.c @@ -163,6 +163,11 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar) spin_lock_irqsave(&fsl_lbc_lock, flags); out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar); + /* + * Dummy read required to ensure that the MAR write takes effect + * before running the pattern + */ + (void) in_be32(&fsl_lbc_ctrl_dev->regs->mar); switch (upm->width) { case 8: