From patchwork Thu Feb 21 16:05:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Tobias Burnus X-Patchwork-Id: 222331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id D180A2C0092 for ; Fri, 22 Feb 2013 03:05:53 +1100 (EST) Comment: DKIM? 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See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Message-ID:Date:From:User-Agent:MIME-Version:To:Subject:Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=LNwGHRzAiK+BMGH11hxsZNOcCHiDfgSbqEUrA7e/7Y/Uu87qPr6UC+A18D9FMt bRcdTgtkBQ4Ocz7h5ymyZFbvxCNbQIHa/6JJxRZKTkG7zRc1V7MgPsWPaZjA5uKt tiZOnFqiCchqc5xcuUQF3wEcQcod56qML9x9snVVvYets=; Received: (qmail 11160 invoked by alias); 21 Feb 2013 16:05:43 -0000 Received: (qmail 11131 invoked by uid 22791); 21 Feb 2013 16:05:39 -0000 X-SWARE-Spam-Status: No, hits=-2.2 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE X-Spam-Check-By: sourceware.org Received: from mx02.qsc.de (HELO mx02.qsc.de) (213.148.130.14) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 21 Feb 2013 16:05:11 +0000 Received: from archimedes.net-b.de (port-92-195-67-77.dynamic.qsc.de [92.195.67.77]) by mx02.qsc.de (Postfix) with ESMTP id 7F13727849; Thu, 21 Feb 2013 17:05:06 +0100 (CET) Message-ID: <512645B2.9040400@net-b.de> Date: Thu, 21 Feb 2013 17:05:06 +0100 From: Tobias Burnus User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130105 Thunderbird/17.0.2 MIME-Version: 1.0 To: gcc patches , gfortran Subject: Fix some texinfo 5.0 warnings in gcc/doc + libiberty Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org This is a follow up to Jakub's patch. With texinfo 5.0 one gets a bunch of warnings. This patch reduces the number of warnings – but there are still warnings to be fixed. This patch solves most of the issues related to mismatches between the item order in the @menu and the actual @nodes. As always, there is the question whether the @node or the item in @menu should be changed. In one case, I had the choice to either add a new item under @menu or to change a @section into @subsection. I did the latter. Tested with "make info" and no new warnings in texinfo 5.0. Additionally, I used texinfo 4.13a with showed no warnings. OK for the trunk? Tobias PS: I tried the following libiberty patch; it fixes a warning with texinfo 5.0. But I do not include it as it fails for some reason with an error with texinfo 4.13: ../../libiberty/libiberty.texi:250: Prev field of node `Functions' not pointed to. ../../libiberty//obstacks.texi:1: This node (Obstacks) has the bad Next. ... gcc/ 2013-02-21 Tobias Burnus * doc/extended.texi (C Extensions): Change order in @menu to match @node. (Other MIPS Built-in Functions): Move last MIPS entry before "picoChip Built-in Functions". (SH Built-in Functions): Move after RX Built-in Functions. * doc/gcc.texi (Introduction): Change order in @menu to match @node. * doc/md.texi (Constraints): Ditto. * gty.texi (Type Information): Ditto. (User-provided marking routines for template types): Make subsection. * doc/invoke.texi (AArch64 Options): Move before "Adapteva Epiphany Options". diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index eb84408..ea4dfc1 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -30,8 +30,8 @@ extensions, accepted by GCC in C90 mode and in C++. * Constructing Calls:: Dispatching a call to another function. * Typeof:: @code{typeof}: referring to the type of an expression. * Conditionals:: Omitting the middle operand of a @samp{?:} expression. -* Long Long:: Double-word integers---@code{long long int}. * __int128:: 128-bit integers---@code{__int128}. +* Long Long:: Double-word integers---@code{long long int}. * Complex:: Data types for complex numbers. * Floating Types:: Additional Floating Types. * Half-Precision:: Half-Precision Floating Point. @@ -40,8 +40,8 @@ extensions, accepted by GCC in C90 mode and in C++. * Fixed-Point:: Fixed-Point Types. * Named Address Spaces::Named address spaces. * Zero Length:: Zero-length arrays. -* Variable Length:: Arrays whose length is computed at run time. * Empty Structures:: Structures with no members. +* Variable Length:: Arrays whose length is computed at run time. * Variadic Macros:: Macros with a variable number of arguments. * Escaped Newlines:: Slightly looser rules for escaped newlines. * Subscripting:: Any array can be subscripted, even if not an lvalue. @@ -50,8 +50,8 @@ extensions, accepted by GCC in C90 mode and in C++. * Compound Literals:: Compound literals give structures, unions or arrays as values. * Designated Inits:: Labeling elements of initializers. -* Cast to Union:: Casting to union type from any member of the union. * Case Ranges:: `case 1 ... 9' and such. +* Cast to Union:: Casting to union type from any member of the union. * Mixed Declarations:: Mixing declarations and code. * Function Attributes:: Declaring that functions have no side effects, or that they can never return. @@ -11653,6 +11653,18 @@ else @end smallexample @end table +@node Other MIPS Built-in Functions +@subsection Other MIPS Built-in Functions + +GCC provides other MIPS-specific built-in functions: + +@table @code +@item void __builtin_mips_cache (int @var{op}, const volatile void *@var{addr}) +Insert a @samp{cache} instruction with operands @var{op} and @var{addr}. +GCC defines the preprocessor macro @code{___GCC_HAVE_BUILTIN_MIPS_CACHE} +when this function is available. +@end table + @node picoChip Built-in Functions @subsection picoChip Built-in Functions @@ -11689,18 +11701,6 @@ implementing assertions. @end table -@node Other MIPS Built-in Functions -@subsection Other MIPS Built-in Functions - -GCC provides other MIPS-specific built-in functions: - -@table @code -@item void __builtin_mips_cache (int @var{op}, const volatile void *@var{addr}) -Insert a @samp{cache} instruction with operands @var{op} and @var{addr}. -GCC defines the preprocessor macro @code{___GCC_HAVE_BUILTIN_MIPS_CACHE} -when this function is available. -@end table - @node PowerPC Built-in Functions @subsection PowerPC Built-in Functions @@ -13791,41 +13791,6 @@ if the VSX instruction set is available. The @samp{vec_vsx_ld} and @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X}, @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. -@node SH Built-in Functions -@subsection SH Built-in Functions -The following built-in functions are supported on the SH1, SH2, SH3 and SH4 -families of processors: - -@deftypefn {Built-in Function} {void} __builtin_set_thread_pointer (void *@var{ptr}) -Sets the @samp{GBR} register to the specified value @var{ptr}. This is usually -used by system code that manages threads and execution contexts. The compiler -normally does not generate code that modifies the contents of @samp{GBR} and -thus the value is preserved across function calls. Changing the @samp{GBR} -value in user code must be done with caution, since the compiler might use -@samp{GBR} in order to access thread local variables. - -@end deftypefn - -@deftypefn {Built-in Function} {void *} __builtin_thread_pointer (void) -Returns the value that is currently set in the @samp{GBR} register. -Memory loads and stores that use the thread pointer as a base address are -turned into @samp{GBR} based displacement loads and stores, if possible. -For example: -@smallexample -struct my_tcb -@{ - int a, b, c, d, e; -@}; - -int get_tcb_value (void) -@{ - // Generate @samp{mov.l @@(8,gbr),r0} instruction - return ((my_tcb*)__builtin_thread_pointer ())->c; -@} - -@end smallexample -@end deftypefn - @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in @@ -13941,6 +13906,41 @@ bit in the processor status word. Generates the @code{wait} machine instruction. @end deftypefn +@node SH Built-in Functions +@subsection SH Built-in Functions +The following built-in functions are supported on the SH1, SH2, SH3 and SH4 +families of processors: + +@deftypefn {Built-in Function} {void} __builtin_set_thread_pointer (void *@var{ptr}) +Sets the @samp{GBR} register to the specified value @var{ptr}. This is usually +used by system code that manages threads and execution contexts. The compiler +normally does not generate code that modifies the contents of @samp{GBR} and +thus the value is preserved across function calls. Changing the @samp{GBR} +value in user code must be done with caution, since the compiler might use +@samp{GBR} in order to access thread local variables. + +@end deftypefn + +@deftypefn {Built-in Function} {void *} __builtin_thread_pointer (void) +Returns the value that is currently set in the @samp{GBR} register. +Memory loads and stores that use the thread pointer as a base address are +turned into @samp{GBR} based displacement loads and stores, if possible. +For example: +@smallexample +struct my_tcb +@{ + int a, b, c, d, e; +@}; + +int get_tcb_value (void) +@{ + // Generate @samp{mov.l @@(8,gbr),r0} instruction + return ((my_tcb*)__builtin_thread_pointer ())->c; +@} + +@end smallexample +@end deftypefn + @node SPARC VIS Built-in Functions @subsection SPARC VIS Built-in Functions diff --git a/gcc/doc/gcc.texi b/gcc/doc/gcc.texi index 8f6f11f..02b81cf 100644 --- a/gcc/doc/gcc.texi +++ b/gcc/doc/gcc.texi @@ -132,8 +132,8 @@ Introduction, gccint, GNU Compiler Collection (GCC) Internals}. * Standards:: Language standards supported by GCC. * Invoking GCC:: Command options supported by @samp{gcc}. * C Implementation:: How GCC implements the ISO C specification. -* C Extensions:: GNU extensions to the C language family. * C++ Implementation:: How GCC implements the ISO C++ specification. +* C Extensions:: GNU extensions to the C language family. * C++ Extensions:: GNU extensions to the C++ language. * Objective-C:: GNU Objective-C runtime features. * Compatibility:: Binary Compatibility diff --git a/gcc/doc/gty.texi b/gcc/doc/gty.texi index a752178..82e8e4f 100644 --- a/gcc/doc/gty.texi +++ b/gcc/doc/gty.texi @@ -87,8 +87,8 @@ data members. @menu * GTY Options:: What goes inside a @code{GTY(())}. -* GGC Roots:: Making global variables GGC roots. * User GC:: Adding user-provided GC marking routines. +* GGC Roots:: Making global variables GGC roots. * Files:: How the generated files work. * Invoking the garbage collector:: How to invoke the garbage collector. * Troubleshooting:: When something does not work as expected. @@ -515,7 +515,7 @@ Note that the rules for the pointer walker @code{gt_pch_nx (my_struct case, the operation @code{op} must be applied to the @emph{address} of every pointer field. -@section User-provided marking routines for template types +@subsection User-provided marking routines for template types When a template type @code{TP} is marked with @code{GTY}, all instances of that type are considered user-provided types. This means that the individual instances of @code{TP} do not need to be marked diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cadee04..66a4686 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -10853,6 +10853,125 @@ platform. * zSeries Options:: @end menu +@node AArch64 Options +@subsection AArch64 Options +@cindex AArch64 Options + +These options are defined for AArch64 implementations: + +@table @gcctabopt + +@item -mbig-endian +@opindex mbig-endian +Generate big-endian code. This is the default when GCC is configured for an +@samp{aarch64_be-*-*} target. + +@item -mgeneral-regs-only +@opindex mgeneral-regs-only +Generate code which uses only the general registers. + +@item -mlittle-endian +@opindex mlittle-endian +Generate little-endian code. This is the default when GCC is configured for an +@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target. + +@item -mcmodel=tiny +@opindex mcmodel=tiny +Generate code for the tiny code model. The program and its statically defined +symbols must be within 1GB of each other. Pointers are 64 bits. Programs can +be statically or dynamically linked. This model is not fully implemented and +mostly treated as @samp{small}. + +@item -mcmodel=small +@opindex mcmodel=small +Generate code for the small code model. The program and its statically defined +symbols must be within 4GB of each other. Pointers are 64 bits. Programs can +be statically or dynamically linked. This is the default code model. + +@item -mcmodel=large +@opindex mcmodel=large +Generate code for the large code model. This makes no assumptions about +addresses and sizes of sections. Pointers are 64 bits. Programs can be +statically linked only. + +@item -mstrict-align +@opindex mstrict-align +Do not assume that unaligned memory references will be handled by the system. + +@item -momit-leaf-frame-pointer +@itemx -mno-omit-leaf-frame-pointer +@opindex momit-leaf-frame-pointer +@opindex mno-omit-leaf-frame-pointer +Omit or keep the frame pointer in leaf functions. The former behaviour is the +default. + +@item -mtls-dialect=desc +@opindex mtls-dialect=desc +Use TLS descriptors as the thread-local storage mechanism for dynamic accesses +of TLS variables. This is the default. + +@item -mtls-dialect=traditional +@opindex mtls-dialect=traditional +Use traditional TLS as the thread-local storage mechanism for dynamic accesses +of TLS variables. + +@item -march=@var{name} +@opindex march +Specify the name of the target architecture, optionally suffixed by one or +more feature modifiers. This option has the form +@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the +only value for @var{arch} is @samp{armv8-a}. The possible values for +@var{feature} are documented in the sub-section below. + +Where conflicting feature modifiers are specified, the right-most feature is +used. + +GCC uses this name to determine what kind of instructions it can emit when +generating assembly code. This option can be used in conjunction with or +instead of the @option{-mcpu=} option. + +@item -mcpu=@var{name} +@opindex mcpu +Specify the name of the target processor, optionally suffixed by one or more +feature modifiers. This option has the form +@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the +possible values for @var{cpu} are @samp{generic}, @samp{large}. The +possible values for @var{feature} are documented in the sub-section +below. + +Where conflicting feature modifiers are specified, the right-most feature is +used. + +GCC uses this name to determine what kind of instructions it can emit when +generating assembly code. + +@item -mtune=@var{name} +@opindex mtune +Specify the name of the processor to tune the performance for. The code will +be tuned as if the target processor were of the type specified in this option, +but still using instructions compatible with the target processor specified +by a @option{-mcpu=} option. This option cannot be suffixed by feature +modifiers. + +@end table + +@subsubsection @option{-march} and @option{-mcpu} feature modifiers +@cindex @option{-march} feature modifiers +@cindex @option{-mcpu} feature modifiers +Feature modifiers used with @option{-march} and @option{-mcpu} can be one +the following: + +@table @samp +@item crypto +Enable Crypto extension. This implies Advanced SIMD is enabled. +@item fp +Enable floating-point instructions. +@item simd +Enable Advanced SIMD instructions. This implies floating-point instructions +are enabled. This is the default for all current possible values for options +@option{-march} and @option{-mcpu=}. +@end table + @node Adapteva Epiphany Options @subsection Adapteva Epiphany Options @@ -11009,125 +11128,6 @@ purpose. The default is @option{-m1reg-none}. @end table -@node AArch64 Options -@subsection AArch64 Options -@cindex AArch64 Options - -These options are defined for AArch64 implementations: - -@table @gcctabopt - -@item -mbig-endian -@opindex mbig-endian -Generate big-endian code. This is the default when GCC is configured for an -@samp{aarch64_be-*-*} target. - -@item -mgeneral-regs-only -@opindex mgeneral-regs-only -Generate code which uses only the general registers. - -@item -mlittle-endian -@opindex mlittle-endian -Generate little-endian code. This is the default when GCC is configured for an -@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target. - -@item -mcmodel=tiny -@opindex mcmodel=tiny -Generate code for the tiny code model. The program and its statically defined -symbols must be within 1GB of each other. Pointers are 64 bits. Programs can -be statically or dynamically linked. This model is not fully implemented and -mostly treated as @samp{small}. - -@item -mcmodel=small -@opindex mcmodel=small -Generate code for the small code model. The program and its statically defined -symbols must be within 4GB of each other. Pointers are 64 bits. Programs can -be statically or dynamically linked. This is the default code model. - -@item -mcmodel=large -@opindex mcmodel=large -Generate code for the large code model. This makes no assumptions about -addresses and sizes of sections. Pointers are 64 bits. Programs can be -statically linked only. - -@item -mstrict-align -@opindex mstrict-align -Do not assume that unaligned memory references will be handled by the system. - -@item -momit-leaf-frame-pointer -@itemx -mno-omit-leaf-frame-pointer -@opindex momit-leaf-frame-pointer -@opindex mno-omit-leaf-frame-pointer -Omit or keep the frame pointer in leaf functions. The former behaviour is the -default. - -@item -mtls-dialect=desc -@opindex mtls-dialect=desc -Use TLS descriptors as the thread-local storage mechanism for dynamic accesses -of TLS variables. This is the default. - -@item -mtls-dialect=traditional -@opindex mtls-dialect=traditional -Use traditional TLS as the thread-local storage mechanism for dynamic accesses -of TLS variables. - -@item -march=@var{name} -@opindex march -Specify the name of the target architecture, optionally suffixed by one or -more feature modifiers. This option has the form -@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the -only value for @var{arch} is @samp{armv8-a}. The possible values for -@var{feature} are documented in the sub-section below. - -Where conflicting feature modifiers are specified, the right-most feature is -used. - -GCC uses this name to determine what kind of instructions it can emit when -generating assembly code. This option can be used in conjunction with or -instead of the @option{-mcpu=} option. - -@item -mcpu=@var{name} -@opindex mcpu -Specify the name of the target processor, optionally suffixed by one or more -feature modifiers. This option has the form -@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the -possible values for @var{cpu} are @samp{generic}, @samp{large}. The -possible values for @var{feature} are documented in the sub-section -below. - -Where conflicting feature modifiers are specified, the right-most feature is -used. - -GCC uses this name to determine what kind of instructions it can emit when -generating assembly code. - -@item -mtune=@var{name} -@opindex mtune -Specify the name of the processor to tune the performance for. The code will -be tuned as if the target processor were of the type specified in this option, -but still using instructions compatible with the target processor specified -by a @option{-mcpu=} option. This option cannot be suffixed by feature -modifiers. - -@end table - -@subsubsection @option{-march} and @option{-mcpu} feature modifiers -@cindex @option{-march} feature modifiers -@cindex @option{-mcpu} feature modifiers -Feature modifiers used with @option{-march} and @option{-mcpu} can be one -the following: - -@table @samp -@item crypto -Enable Crypto extension. This implies Advanced SIMD is enabled. -@item fp -Enable floating-point instructions. -@item simd -Enable Advanced SIMD instructions. This implies floating-point instructions -are enabled. This is the default for all current possible values for options -@option{-march} and @option{-mcpu=}. -@end table - @node ARM Options @subsection ARM Options @cindex ARM options diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 9739e4f..63ec92f 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1079,8 +1079,8 @@ the addressing register. * Multi-Alternative:: When an insn has two alternative constraint-patterns. * Class Preferences:: Constraints guide which hard register to put things in. * Modifiers:: More precise control over effects of constraints. -* Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute. * Machine Constraints:: Existing constraints for some particular machines. +* Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute. * Define Constraints:: How to define machine-specific constraints. * C Constraint Interface:: How to test constraints from C code. @end menu diff --git a/libiberty/libiberty.texi b/libiberty/libiberty.texi index 74f70d2..5a72f13 100644 --- a/libiberty/libiberty.texi +++ b/libiberty/libiberty.texi @@ -80,10 +80,10 @@ License; for more information, see @ref{Library Copying}. * Overview:: Overview of available function groups. -* Functions:: Available functions, macros, and global variables. - * Obstacks:: Object Stacks. +* Functions:: Available functions, macros, and global variables. + * Licenses:: The various licenses under which libiberty sources are distributed. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index eb84408..ea4dfc1 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -30,8 +30,8 @@ extensions, accepted by GCC in C90 mode and in C++. * Constructing Calls:: Dispatching a call to another function. * Typeof:: @code{typeof}: referring to the type of an expression. * Conditionals:: Omitting the middle operand of a @samp{?:} expression. -* Long Long:: Double-word integers---@code{long long int}. * __int128:: 128-bit integers---@code{__int128}. +* Long Long:: Double-word integers---@code{long long int}. * Complex:: Data types for complex numbers. * Floating Types:: Additional Floating Types. * Half-Precision:: Half-Precision Floating Point. @@ -40,8 +40,8 @@ extensions, accepted by GCC in C90 mode and in C++. * Fixed-Point:: Fixed-Point Types. * Named Address Spaces::Named address spaces. * Zero Length:: Zero-length arrays. -* Variable Length:: Arrays whose length is computed at run time. * Empty Structures:: Structures with no members. +* Variable Length:: Arrays whose length is computed at run time. * Variadic Macros:: Macros with a variable number of arguments. * Escaped Newlines:: Slightly looser rules for escaped newlines. * Subscripting:: Any array can be subscripted, even if not an lvalue. @@ -50,8 +50,8 @@ extensions, accepted by GCC in C90 mode and in C++. * Compound Literals:: Compound literals give structures, unions or arrays as values. * Designated Inits:: Labeling elements of initializers. -* Cast to Union:: Casting to union type from any member of the union. * Case Ranges:: `case 1 ... 9' and such. +* Cast to Union:: Casting to union type from any member of the union. * Mixed Declarations:: Mixing declarations and code. * Function Attributes:: Declaring that functions have no side effects, or that they can never return. @@ -11653,6 +11653,18 @@ else @end smallexample @end table +@node Other MIPS Built-in Functions +@subsection Other MIPS Built-in Functions + +GCC provides other MIPS-specific built-in functions: + +@table @code +@item void __builtin_mips_cache (int @var{op}, const volatile void *@var{addr}) +Insert a @samp{cache} instruction with operands @var{op} and @var{addr}. +GCC defines the preprocessor macro @code{___GCC_HAVE_BUILTIN_MIPS_CACHE} +when this function is available. +@end table + @node picoChip Built-in Functions @subsection picoChip Built-in Functions @@ -11689,18 +11701,6 @@ implementing assertions. @end table -@node Other MIPS Built-in Functions -@subsection Other MIPS Built-in Functions - -GCC provides other MIPS-specific built-in functions: - -@table @code -@item void __builtin_mips_cache (int @var{op}, const volatile void *@var{addr}) -Insert a @samp{cache} instruction with operands @var{op} and @var{addr}. -GCC defines the preprocessor macro @code{___GCC_HAVE_BUILTIN_MIPS_CACHE} -when this function is available. -@end table - @node PowerPC Built-in Functions @subsection PowerPC Built-in Functions @@ -13791,41 +13791,6 @@ if the VSX instruction set is available. The @samp{vec_vsx_ld} and @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X}, @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. -@node SH Built-in Functions -@subsection SH Built-in Functions -The following built-in functions are supported on the SH1, SH2, SH3 and SH4 -families of processors: - -@deftypefn {Built-in Function} {void} __builtin_set_thread_pointer (void *@var{ptr}) -Sets the @samp{GBR} register to the specified value @var{ptr}. This is usually -used by system code that manages threads and execution contexts. The compiler -normally does not generate code that modifies the contents of @samp{GBR} and -thus the value is preserved across function calls. Changing the @samp{GBR} -value in user code must be done with caution, since the compiler might use -@samp{GBR} in order to access thread local variables. - -@end deftypefn - -@deftypefn {Built-in Function} {void *} __builtin_thread_pointer (void) -Returns the value that is currently set in the @samp{GBR} register. -Memory loads and stores that use the thread pointer as a base address are -turned into @samp{GBR} based displacement loads and stores, if possible. -For example: -@smallexample -struct my_tcb -@{ - int a, b, c, d, e; -@}; - -int get_tcb_value (void) -@{ - // Generate @samp{mov.l @@(8,gbr),r0} instruction - return ((my_tcb*)__builtin_thread_pointer ())->c; -@} - -@end smallexample -@end deftypefn - @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in @@ -13941,6 +13906,41 @@ bit in the processor status word. Generates the @code{wait} machine instruction. @end deftypefn +@node SH Built-in Functions +@subsection SH Built-in Functions +The following built-in functions are supported on the SH1, SH2, SH3 and SH4 +families of processors: + +@deftypefn {Built-in Function} {void} __builtin_set_thread_pointer (void *@var{ptr}) +Sets the @samp{GBR} register to the specified value @var{ptr}. This is usually +used by system code that manages threads and execution contexts. The compiler +normally does not generate code that modifies the contents of @samp{GBR} and +thus the value is preserved across function calls. Changing the @samp{GBR} +value in user code must be done with caution, since the compiler might use +@samp{GBR} in order to access thread local variables. + +@end deftypefn + +@deftypefn {Built-in Function} {void *} __builtin_thread_pointer (void) +Returns the value that is currently set in the @samp{GBR} register. +Memory loads and stores that use the thread pointer as a base address are +turned into @samp{GBR} based displacement loads and stores, if possible. +For example: +@smallexample +struct my_tcb +@{ + int a, b, c, d, e; +@}; + +int get_tcb_value (void) +@{ + // Generate @samp{mov.l @@(8,gbr),r0} instruction + return ((my_tcb*)__builtin_thread_pointer ())->c; +@} + +@end smallexample +@end deftypefn + @node SPARC VIS Built-in Functions @subsection SPARC VIS Built-in Functions diff --git a/gcc/doc/gcc.texi b/gcc/doc/gcc.texi index 8f6f11f..02b81cf 100644 --- a/gcc/doc/gcc.texi +++ b/gcc/doc/gcc.texi @@ -132,8 +132,8 @@ Introduction, gccint, GNU Compiler Collection (GCC) Internals}. * Standards:: Language standards supported by GCC. * Invoking GCC:: Command options supported by @samp{gcc}. * C Implementation:: How GCC implements the ISO C specification. -* C Extensions:: GNU extensions to the C language family. * C++ Implementation:: How GCC implements the ISO C++ specification. +* C Extensions:: GNU extensions to the C language family. * C++ Extensions:: GNU extensions to the C++ language. * Objective-C:: GNU Objective-C runtime features. * Compatibility:: Binary Compatibility diff --git a/gcc/doc/gty.texi b/gcc/doc/gty.texi index a752178..82e8e4f 100644 --- a/gcc/doc/gty.texi +++ b/gcc/doc/gty.texi @@ -87,8 +87,8 @@ data members. @menu * GTY Options:: What goes inside a @code{GTY(())}. -* GGC Roots:: Making global variables GGC roots. * User GC:: Adding user-provided GC marking routines. +* GGC Roots:: Making global variables GGC roots. * Files:: How the generated files work. * Invoking the garbage collector:: How to invoke the garbage collector. * Troubleshooting:: When something does not work as expected. @@ -515,7 +515,7 @@ Note that the rules for the pointer walker @code{gt_pch_nx (my_struct case, the operation @code{op} must be applied to the @emph{address} of every pointer field. -@section User-provided marking routines for template types +@subsection User-provided marking routines for template types When a template type @code{TP} is marked with @code{GTY}, all instances of that type are considered user-provided types. This means that the individual instances of @code{TP} do not need to be marked diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cadee04..66a4686 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -10853,6 +10853,125 @@ platform. * zSeries Options:: @end menu +@node AArch64 Options +@subsection AArch64 Options +@cindex AArch64 Options + +These options are defined for AArch64 implementations: + +@table @gcctabopt + +@item -mbig-endian +@opindex mbig-endian +Generate big-endian code. This is the default when GCC is configured for an +@samp{aarch64_be-*-*} target. + +@item -mgeneral-regs-only +@opindex mgeneral-regs-only +Generate code which uses only the general registers. + +@item -mlittle-endian +@opindex mlittle-endian +Generate little-endian code. This is the default when GCC is configured for an +@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target. + +@item -mcmodel=tiny +@opindex mcmodel=tiny +Generate code for the tiny code model. The program and its statically defined +symbols must be within 1GB of each other. Pointers are 64 bits. Programs can +be statically or dynamically linked. This model is not fully implemented and +mostly treated as @samp{small}. + +@item -mcmodel=small +@opindex mcmodel=small +Generate code for the small code model. The program and its statically defined +symbols must be within 4GB of each other. Pointers are 64 bits. Programs can +be statically or dynamically linked. This is the default code model. + +@item -mcmodel=large +@opindex mcmodel=large +Generate code for the large code model. This makes no assumptions about +addresses and sizes of sections. Pointers are 64 bits. Programs can be +statically linked only. + +@item -mstrict-align +@opindex mstrict-align +Do not assume that unaligned memory references will be handled by the system. + +@item -momit-leaf-frame-pointer +@itemx -mno-omit-leaf-frame-pointer +@opindex momit-leaf-frame-pointer +@opindex mno-omit-leaf-frame-pointer +Omit or keep the frame pointer in leaf functions. The former behaviour is the +default. + +@item -mtls-dialect=desc +@opindex mtls-dialect=desc +Use TLS descriptors as the thread-local storage mechanism for dynamic accesses +of TLS variables. This is the default. + +@item -mtls-dialect=traditional +@opindex mtls-dialect=traditional +Use traditional TLS as the thread-local storage mechanism for dynamic accesses +of TLS variables. + +@item -march=@var{name} +@opindex march +Specify the name of the target architecture, optionally suffixed by one or +more feature modifiers. This option has the form +@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the +only value for @var{arch} is @samp{armv8-a}. The possible values for +@var{feature} are documented in the sub-section below. + +Where conflicting feature modifiers are specified, the right-most feature is +used. + +GCC uses this name to determine what kind of instructions it can emit when +generating assembly code. This option can be used in conjunction with or +instead of the @option{-mcpu=} option. + +@item -mcpu=@var{name} +@opindex mcpu +Specify the name of the target processor, optionally suffixed by one or more +feature modifiers. This option has the form +@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the +possible values for @var{cpu} are @samp{generic}, @samp{large}. The +possible values for @var{feature} are documented in the sub-section +below. + +Where conflicting feature modifiers are specified, the right-most feature is +used. + +GCC uses this name to determine what kind of instructions it can emit when +generating assembly code. + +@item -mtune=@var{name} +@opindex mtune +Specify the name of the processor to tune the performance for. The code will +be tuned as if the target processor were of the type specified in this option, +but still using instructions compatible with the target processor specified +by a @option{-mcpu=} option. This option cannot be suffixed by feature +modifiers. + +@end table + +@subsubsection @option{-march} and @option{-mcpu} feature modifiers +@cindex @option{-march} feature modifiers +@cindex @option{-mcpu} feature modifiers +Feature modifiers used with @option{-march} and @option{-mcpu} can be one +the following: + +@table @samp +@item crypto +Enable Crypto extension. This implies Advanced SIMD is enabled. +@item fp +Enable floating-point instructions. +@item simd +Enable Advanced SIMD instructions. This implies floating-point instructions +are enabled. This is the default for all current possible values for options +@option{-march} and @option{-mcpu=}. +@end table + @node Adapteva Epiphany Options @subsection Adapteva Epiphany Options @@ -11009,125 +11128,6 @@ purpose. The default is @option{-m1reg-none}. @end table -@node AArch64 Options -@subsection AArch64 Options -@cindex AArch64 Options - -These options are defined for AArch64 implementations: - -@table @gcctabopt - -@item -mbig-endian -@opindex mbig-endian -Generate big-endian code. This is the default when GCC is configured for an -@samp{aarch64_be-*-*} target. - -@item -mgeneral-regs-only -@opindex mgeneral-regs-only -Generate code which uses only the general registers. - -@item -mlittle-endian -@opindex mlittle-endian -Generate little-endian code. This is the default when GCC is configured for an -@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target. - -@item -mcmodel=tiny -@opindex mcmodel=tiny -Generate code for the tiny code model. The program and its statically defined -symbols must be within 1GB of each other. Pointers are 64 bits. Programs can -be statically or dynamically linked. This model is not fully implemented and -mostly treated as @samp{small}. - -@item -mcmodel=small -@opindex mcmodel=small -Generate code for the small code model. The program and its statically defined -symbols must be within 4GB of each other. Pointers are 64 bits. Programs can -be statically or dynamically linked. This is the default code model. - -@item -mcmodel=large -@opindex mcmodel=large -Generate code for the large code model. This makes no assumptions about -addresses and sizes of sections. Pointers are 64 bits. Programs can be -statically linked only. - -@item -mstrict-align -@opindex mstrict-align -Do not assume that unaligned memory references will be handled by the system. - -@item -momit-leaf-frame-pointer -@itemx -mno-omit-leaf-frame-pointer -@opindex momit-leaf-frame-pointer -@opindex mno-omit-leaf-frame-pointer -Omit or keep the frame pointer in leaf functions. The former behaviour is the -default. - -@item -mtls-dialect=desc -@opindex mtls-dialect=desc -Use TLS descriptors as the thread-local storage mechanism for dynamic accesses -of TLS variables. This is the default. - -@item -mtls-dialect=traditional -@opindex mtls-dialect=traditional -Use traditional TLS as the thread-local storage mechanism for dynamic accesses -of TLS variables. - -@item -march=@var{name} -@opindex march -Specify the name of the target architecture, optionally suffixed by one or -more feature modifiers. This option has the form -@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the -only value for @var{arch} is @samp{armv8-a}. The possible values for -@var{feature} are documented in the sub-section below. - -Where conflicting feature modifiers are specified, the right-most feature is -used. - -GCC uses this name to determine what kind of instructions it can emit when -generating assembly code. This option can be used in conjunction with or -instead of the @option{-mcpu=} option. - -@item -mcpu=@var{name} -@opindex mcpu -Specify the name of the target processor, optionally suffixed by one or more -feature modifiers. This option has the form -@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the -possible values for @var{cpu} are @samp{generic}, @samp{large}. The -possible values for @var{feature} are documented in the sub-section -below. - -Where conflicting feature modifiers are specified, the right-most feature is -used. - -GCC uses this name to determine what kind of instructions it can emit when -generating assembly code. - -@item -mtune=@var{name} -@opindex mtune -Specify the name of the processor to tune the performance for. The code will -be tuned as if the target processor were of the type specified in this option, -but still using instructions compatible with the target processor specified -by a @option{-mcpu=} option. This option cannot be suffixed by feature -modifiers. - -@end table - -@subsubsection @option{-march} and @option{-mcpu} feature modifiers -@cindex @option{-march} feature modifiers -@cindex @option{-mcpu} feature modifiers -Feature modifiers used with @option{-march} and @option{-mcpu} can be one -the following: - -@table @samp -@item crypto -Enable Crypto extension. This implies Advanced SIMD is enabled. -@item fp -Enable floating-point instructions. -@item simd -Enable Advanced SIMD instructions. This implies floating-point instructions -are enabled. This is the default for all current possible values for options -@option{-march} and @option{-mcpu=}. -@end table - @node ARM Options @subsection ARM Options @cindex ARM options diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 9739e4f..63ec92f 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -1079,8 +1079,8 @@ the addressing register. * Multi-Alternative:: When an insn has two alternative constraint-patterns. * Class Preferences:: Constraints guide which hard register to put things in. * Modifiers:: More precise control over effects of constraints. -* Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute. * Machine Constraints:: Existing constraints for some particular machines. +* Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute. * Define Constraints:: How to define machine-specific constraints. * C Constraint Interface:: How to test constraints from C code. @end menu