From patchwork Thu Feb 21 11:06:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sonic Zhang X-Patchwork-Id: 222253 X-Patchwork-Delegate: sonic.adi@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 642AE2C0082 for ; Thu, 21 Feb 2013 22:08:23 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 153D24A15C; Thu, 21 Feb 2013 12:06:37 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 91bozrjQZF9Z; Thu, 21 Feb 2013 12:06:36 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 077D84A188; Thu, 21 Feb 2013 12:05:17 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F23A64A12F for ; Thu, 21 Feb 2013 12:04:50 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id D-qRAocyrsa6 for ; Thu, 21 Feb 2013 12:04:47 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from tx2outboundpool.messaging.microsoft.com (tx2ehsobe003.messaging.microsoft.com [65.55.88.13]) by theia.denx.de (Postfix) with ESMTPS id 699234A148 for ; Thu, 21 Feb 2013 12:04:34 +0100 (CET) Received: from mail68-tx2-R.bigfish.com (10.9.14.254) by TX2EHSOBE003.bigfish.com (10.9.40.23) with Microsoft SMTP Server id 14.1.225.23; Thu, 21 Feb 2013 11:04:30 +0000 Received: from mail68-tx2 (localhost [127.0.0.1]) by mail68-tx2-R.bigfish.com (Postfix) with ESMTP id 539AE4E00F7; Thu, 21 Feb 2013 11:04:30 +0000 (UTC) X-Forefront-Antispam-Report: CIP:137.71.25.55; KIP:(null); UIP:(null); IPV:NLI; H:nwd2mta1.analog.com; RD:nwd2mail10.analog.com; EFVD:NLI X-SpamScore: 12 X-BigFish: VS12(zzzz1f42h1ee6h1ce5h1202h1e76h1d1ah1cabh1d2ahzz8275bhz2ei87h2a8h668h839hd24he5bh1288h12a5h12a9h12bdh12e5h1354h137ah139eh13b6h13eah1441h1504h1537h15a8h162dh1631h1758h17eeh1898h18e1h1946h19b5hff4m1355m129fi1155h) Received-SPF: neutral (mail68-tx2: 137.71.25.55 is neither permitted nor denied by domain of gmail.com) client-ip=137.71.25.55; envelope-from=sonic.adi@gmail.com; helo=nwd2mta1.analog.com ; 1.analog.com ; X-FB-DOMAIN-IP-MATCH: fail Received: from mail68-tx2 (localhost.localdomain [127.0.0.1]) by mail68-tx2 (MessageSwitch) id 1361444668345291_2672; Thu, 21 Feb 2013 11:04:28 +0000 (UTC) Received: from TX2EHSMHS015.bigfish.com (unknown [10.9.14.248]) by mail68-tx2.bigfish.com (Postfix) with ESMTP id 4601A460070; Thu, 21 Feb 2013 11:04:28 +0000 (UTC) Received: from nwd2mta1.analog.com (137.71.25.55) by TX2EHSMHS015.bigfish.com (10.9.99.115) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 21 Feb 2013 11:04:21 +0000 Received: from NWD2HUBCAS5.ad.analog.com (nwd2hubcas5.ad.analog.com [10.64.72.161]) by nwd2mta1.analog.com (8.13.8/8.13.8) with ESMTP id r1LB4Kv5003236 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL); Thu, 21 Feb 2013 03:04:21 -0800 Received: from zeus.spd.analog.com (10.64.82.11) by NWD2HUBCAS5.ad.analog.com (10.64.72.161) with Microsoft SMTP Server id 14.2.328.9; Thu, 21 Feb 2013 06:04:20 -0500 Received: from linux.site ([10.99.22.20]) by zeus.spd.analog.com (8.14.5/8.14.5) with ESMTP id r1LB4JII019820; Thu, 21 Feb 2013 06:04:19 -0500 Received: from localhost.localdomain (unknown [10.99.22.81]) by linux.site (Postfix) with ESMTP id 7A13B42CE143; Wed, 20 Feb 2013 20:35:48 -0700 (MST) From: Sonic Zhang To: Wolfgang Denk , Date: Thu, 21 Feb 2013 19:06:43 +0800 Message-ID: <1361444809-22035-6-git-send-email-sonic.adi@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1361444809-22035-1-git-send-email-sonic.adi@gmail.com> References: <1361444809-22035-1-git-send-email-sonic.adi@gmail.com> MIME-Version: 1.0 Cc: u-boot-devel@blackfin.uclinux.org, Sonic Zhang Subject: [U-Boot] [PATCH v4 05/11] blackfin: bf60x: support big cplb page X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Bob Liu BF60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them. So that bf609-ezkit can use it's 128M memory. Signed-off-by: Bob Liu Signed-off-by: Sonic Zhang --- Changes in v4: None Changes in v3: None Changes in v2: - Fix all checkpatch issues. - Replace run-time variable with additional macros when adding 4M byte CPLB entries. arch/blackfin/include/asm/cplb.h | 31 +++++++++++++++++++++++++++---- arch/blackfin/lib/board.c | 19 +++++++++++++++++-- 2 files changed, 44 insertions(+), 6 deletions(-) diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index cc21e93..420380d 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h @@ -46,8 +46,13 @@ #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL /* Data Attibutes*/ - -#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#if defined(__ADSPBF60x__) +#define SDRAM_IGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | \ + CPLB_USER_RD | CPLB_VALID) +#else +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | \ + CPLB_USER_RD | CPLB_VALID) +#endif #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) @@ -59,14 +64,32 @@ #endif #ifdef CONFIG_DCACHE_WB /*Write Back Policy */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#if defined(__ADSPBF60x__) +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \ + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \ + CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#else +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \ + CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \ + CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#endif #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #else /*Write Through */ -#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) +#if defined(__ADSPBF60x__) +#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \ + CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \ + CPLB_USER_WR | CPLB_VALID | \ + ANOMALY_05000158_WORKAROUND) +#else +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \ + CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \ + CPLB_USER_WR | CPLB_VALID | \ + ANOMALY_05000158_WORKAROUND) +#endif #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND) #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND) diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 098f685..288dc82 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -96,6 +96,13 @@ static void display_global_data(void) #define CPLB_PAGE_SIZE (4 * 1024 * 1024) #define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1)) +#if defined(__ADSPBF60x__) +#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024) +#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1)) +#else +#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE +#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK +#endif void init_cplbtables(void) { volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA; @@ -127,6 +134,11 @@ void init_cplbtables(void) icplb_add(0xFFA00000, L1_IMEMORY); dcplb_add(0xFF800000, L1_DMEMORY); ++i; +#if defined(__ADSPBF60x__) + icplb_add(0x0, 0x0); + dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU); + ++i; +#endif if (CONFIG_MEM_SIZE) { uint32_t mbase = CONFIG_SYS_MONITOR_BASE; @@ -150,9 +162,11 @@ void init_cplbtables(void) } } +#ifndef __ADSPBF60x__ icplb_add(0x20000000, SDRAM_INON_CHBL); dcplb_add(0x20000000, SDRAM_EBIU); ++i; +#endif /* Add entries for the rest of external RAM up to the bootrom */ extern_memory = 0; @@ -167,10 +181,11 @@ void init_cplbtables(void) ++i; #endif - while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) { + while (i < 16 && extern_memory < + (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) { icplb_add(extern_memory, SDRAM_IGENERIC); dcplb_add(extern_memory, SDRAM_DGENERIC); - extern_memory += CPLB_PAGE_SIZE; + extern_memory += CPLB_EX_PAGE_SIZE; ++i; } while (i < 16) {