diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 97aedc5..84ae9e8 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -21,8 +21,42 @@
 #include "cpu.h"
 #include "qemu/host-utils.h"
 
-#define D(x)
-#define DMMU(x)
+#undef DEBUG_MB
+#undef DEBUG_MB_MMU
+
+#ifdef DEBUG_MB
+static const bool debug_helper = true;
+#else
+static const bool debug_helper;
+#endif
+
+#ifdef DEBUG_MB_MMU
+static const bool debug_mmu = true;
+#else
+static const bool debug_mmu;
+#endif
+
+#ifndef CONFIG_USER_ONLY
+static void GCC_FMT_ATTR(1, 2) D_LOG(const char *fmt, ...)
+{
+    if (debug_helper) {
+        va_list ap;
+        va_start(ap, fmt);
+        qemu_log_vprintf(fmt, ap);
+        va_end(ap);
+    }
+}
+
+static void GCC_FMT_ATTR(1, 2) mmu_log(const char *fmt, ...)
+{
+    if (debug_mmu) {
+        va_list ap;
+        va_start(ap, fmt);
+        qemu_log_vprintf(fmt, ap);
+        va_end(ap);
+    }
+}
+#endif
 
 #if defined(CONFIG_USER_ONLY)
 
@@ -70,13 +104,13 @@ int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
             vaddr = address & TARGET_PAGE_MASK;
             paddr = lu.paddr + vaddr - lu.vaddr;
 
-            DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
-                     mmu_idx, vaddr, paddr, lu.prot));
+            mmu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
+                    mmu_idx, vaddr, paddr, lu.prot);
             tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
             r = 0;
         } else {
             env->sregs[SR_EAR] = address;
-            DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));
+            mmu_log("mmu=%d miss v=%x\n", mmu_idx, address);
 
             switch (lu.err) {
                 case ERR_PROT:
@@ -156,7 +190,7 @@ void do_interrupt(CPUMBState *env)
             env->sregs[SR_ESR] &= ~(1 << 12);
             /* Exception breaks branch + dslot sequence?  */
             if (env->iflags & D_FLAG) {
-                D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
+                D_LOG("D_FLAG set at exception bimm=%d\n", env->bimm);
                 env->sregs[SR_ESR] |= 1 << 12 ;
                 env->sregs[SR_BTR] = env->btarget;
 
@@ -171,7 +205,7 @@ void do_interrupt(CPUMBState *env)
                     log_cpu_state_mask(CPU_LOG_INT, env, 0);
                 }
             } else if (env->iflags & IMM_FLAG) {
-                D(qemu_log("IMM_FLAG set at exception\n"));
+                D_LOG("IMM_FLAG set at exception\n");
                 env->regs[17] -= 4;
             }
 
diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
index 53ad263..3373d50 100644
--- a/target-microblaze/mmu.c
+++ b/target-microblaze/mmu.c
@@ -20,7 +20,23 @@
 
 #include "cpu.h"
 
-#define D(x)
+#undef DEBUG_MB
+
+#ifdef DEBUG_MB
+static const bool debug_mmu = true;
+#else
+static const bool debug_mmu;
+#endif
+
+static void GCC_FMT_ATTR(1, 2) D_LOG(const char *fmt, ...)
+{
+    if (debug_mmu) {
+        va_list ap;
+        va_start(ap, fmt);
+        qemu_log_vprintf(fmt, ap);
+        va_end(ap);
+    }
+}
 
 static unsigned int tlb_decode_size(unsigned int f)
 {
@@ -87,7 +103,7 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
 
         /* Lookup and decode.  */
         t = mmu->rams[RAM_TAG][i];
-        D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));
+        D_LOG("TLB %d valid=%d\n", i, t & TLB_VALID);
         if (t & TLB_VALID) {
             tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
             if (tlb_size < TARGET_PAGE_SIZE) {
@@ -98,14 +114,14 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
             mask = ~(tlb_size - 1);
             tlb_tag = t & TLB_EPN_MASK;
             if ((vaddr & mask) != (tlb_tag & mask)) {
-                D(qemu_log("TLB %d vaddr=%x != tag=%x\n",
-                           i, vaddr & mask, tlb_tag & mask));
+                D_LOG("TLB %d vaddr=%x != tag=%x\n",
+                      i, vaddr & mask, tlb_tag & mask);
                 continue;
             }
             if (mmu->tids[i]
                 && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
-                D(qemu_log("TLB %d pid=%x != tid=%x\n",
-                           i, mmu->regs[MMU_R_PID], mmu->tids[i]));
+                D_LOG("TLB %d pid=%x != tid=%x\n",
+                      i, mmu->regs[MMU_R_PID], mmu->tids[i]);
                 continue;
             }
 
@@ -170,8 +186,8 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu,
         }
     }
 done:
-    D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
-              vaddr, rw, tlb_wr, tlb_ex, hit));
+    D_LOG("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
+          vaddr, rw, tlb_wr, tlb_ex, hit);
     return hit;
 }
 
@@ -212,14 +228,14 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
             r = env->mmu.regs[rn];
             break;
     }
-    D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
+    D_LOG("%s rn=%d=%x\n", __func__, rn, r);
     return r;
 }
 
 void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
 {
     unsigned int i;
-    D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
+    D_LOG("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]);
 
     if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
         qemu_log("MMU access on MMU-less system\n");
@@ -240,7 +256,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
             }
             env->mmu.rams[rn & 1][i] = v;
 
-            D(qemu_log("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v));
+            D_LOG("%s ram[%d][%d]=%x\n", __func__, rn & 1, i, v);
             break;
         case MMU_R_ZPR:
             if (env->mmu.c_mmu_tlb_access <= 1) {
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 1c62f3c..0970719 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -23,8 +23,6 @@
 #include "helper.h"
 #include "qemu/host-utils.h"
 
-#define D(x)
-
 #if !defined(CONFIG_USER_ONLY)
 #include "exec/softmmu_exec.h"
 
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 12ea820..87d2a2f 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -31,12 +31,20 @@
 #define DISAS_GNU 1
 #define DISAS_MB 1
 #if DISAS_MB && !SIM_COMPAT
-#  define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
+static const bool debug_disas = true;
 #else
-#  define LOG_DIS(...) do { } while (0)
+static const bool debug_disas;
 #endif
 
-#define D(x)
+static void GCC_FMT_ATTR(1, 2) LOG_DIS(const char *fmt, ...)
+{
+    if (debug_disas) {
+        va_list ap;
+        va_start(ap, fmt);
+        qemu_log_mask(CPU_LOG_TB_IN_ASM, fmt, ap);
+        va_end(ap);
+    }
+}
 
 #define EXTRACT_FIELD(src, start, end) \
             (((src) >> start) & ((1 << (end - start + 1)) - 1))
