From patchwork Wed Feb 20 07:52:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 222026 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8FB172C0085 for ; Wed, 20 Feb 2013 20:56:45 +1100 (EST) Received: from localhost ([::1]:48280 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U84Us-0001nV-Px for incoming@patchwork.ozlabs.org; Wed, 20 Feb 2013 02:53:46 -0500 Received: from eggs.gnu.org ([208.118.235.92]:43824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U84UI-0001MU-Cc for qemu-devel@nongnu.org; Wed, 20 Feb 2013 02:53:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U84UE-0002Es-UJ for qemu-devel@nongnu.org; Wed, 20 Feb 2013 02:53:09 -0500 Received: from mail-da0-f51.google.com ([209.85.210.51]:59388) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U84UE-0002Eg-O9 for qemu-devel@nongnu.org; Wed, 20 Feb 2013 02:53:06 -0500 Received: by mail-da0-f51.google.com with SMTP id n15so3368978dad.38 for ; Tue, 19 Feb 2013 23:53:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=w6yY547xMLnKX35jVnN8LSDb/bKQ4Iv4sZtD7BSO+Pc=; b=YwJK6t8p6Y2QMK9iLWIB2eFbiPrKQmH9QZRk3yeEwt086vVGdc75ohsU0K4TlRanw8 jJ5/hC8Dg194vEcm70VbIfvlvSpsOSfW1UJpXhfjgs10B6PhjLlNcfFtDpKXGDJ5OG3V 3xrqvaiEnTEFSlE8EWOGnX+PpE0kbh3afz/PijG5bKImwfzQNE8L43v8BlhO+8R/k92h YrcVun4xcRfEKsq0Os+I26JenqyfjVluhDBUcrWxED/0B26DFNn5vNr52NU4S4vMtudc 51Y+OqcQPYtKxkF4do8mUcPYjqMnMV5a0JdVMcQZZCGs+UKRSMd4l9WK+ANMOk7GurXZ LJHA== X-Received: by 10.66.8.197 with SMTP id t5mr1051676paa.221.1361346785997; Tue, 19 Feb 2013 23:53:05 -0800 (PST) Received: from anchor.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id c8sm20826347pbq.10.2013.02.19.23.53.04 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 19 Feb 2013 23:53:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Feb 2013 23:52:06 -0800 Message-Id: <1361346746-8511-19-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1361346746-8511-1-git-send-email-rth@twiddle.net> References: <1361346746-8511-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.210.51 Cc: blauwirbel@gmail.com, Peter Maydell , aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 18/38] target-arm: Use mul[us]2 and add2 in umlal et al X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Cc: Peter Maydell Signed-off-by: Richard Henderson --- target-arm/helper.c | 5 ----- target-arm/helper.h | 2 -- target-arm/translate.c | 26 ++++++++++++++------------ 3 files changed, 14 insertions(+), 19 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index e63da57..e97e1a5 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2893,11 +2893,6 @@ uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b) return (a & mask) | (b & ~mask); } -uint32_t HELPER(logicq_cc)(uint64_t val) -{ - return (val >> 32) | (val != 0); -} - /* VFP support. We follow the convention used for VFP instructions: Single precision routines have a "s" suffix, double precision a "d" suffix. */ diff --git a/target-arm/helper.h b/target-arm/helper.h index 8544f82..bca5a5b 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -46,8 +46,6 @@ DEF_HELPER_3(usat16, i32, env, i32, i32) DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) -DEF_HELPER_1(logicq_cc, i32, i64) - DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(exception, void, env, i32) diff --git a/target-arm/translate.c b/target-arm/translate.c index 129f674..efe76d0 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6433,13 +6433,11 @@ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) tcg_temp_free_i64(tmp); } -/* Set N and Z flags from a 64-bit value. */ -static void gen_logicq_cc(TCGv_i64 val) +/* Set N and Z flags from hi|lo. */ +static void gen_logicq_cc(TCGv lo, TCGv hi) { - TCGv tmp = tcg_temp_new_i32(); - gen_helper_logicq_cc(tmp, val); - gen_logic_CC(tmp); - tcg_temp_free_i32(tmp); + tcg_gen_mov_i32(cpu_NF, hi); + tcg_gen_or_i32(cpu_ZF, lo, hi); } /* Load/Store exclusive instructions are implemented by remembering @@ -7219,18 +7217,22 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) tmp = load_reg(s, rs); tmp2 = load_reg(s, rm); if (insn & (1 << 22)) { - tmp64 = gen_muls_i64_i32(tmp, tmp2); + tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2); } else { - tmp64 = gen_mulu_i64_i32(tmp, tmp2); + tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2); } if (insn & (1 << 21)) { /* mult accumulate */ - gen_addq(s, tmp64, rn, rd); + TCGv al = load_reg(s, rn); + TCGv ah = load_reg(s, rd); + tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah); + tcg_temp_free(al); + tcg_temp_free(ah); } if (insn & (1 << 20)) { - gen_logicq_cc(tmp64); + gen_logicq_cc(tmp, tmp2); } - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); + store_reg(s, rn, tmp); + store_reg(s, rd, tmp2); break; default: goto illegal_op;