From patchwork Wed Feb 20 07:52:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 222020 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 726FC2C0082 for ; Wed, 20 Feb 2013 20:31:27 +1100 (EST) Received: from localhost ([::1]:48287 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U84Uw-0001ne-Ca for incoming@patchwork.ozlabs.org; Wed, 20 Feb 2013 02:53:50 -0500 Received: from eggs.gnu.org ([208.118.235.92]:43784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U84UD-00018K-HX for qemu-devel@nongnu.org; Wed, 20 Feb 2013 02:53:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U84U5-0002Ch-KC for qemu-devel@nongnu.org; Wed, 20 Feb 2013 02:53:05 -0500 Received: from mail-pb0-f50.google.com ([209.85.160.50]:59917) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U84U5-0002Cb-Dp for qemu-devel@nongnu.org; Wed, 20 Feb 2013 02:52:57 -0500 Received: by mail-pb0-f50.google.com with SMTP id up1so2745504pbc.9 for ; Tue, 19 Feb 2013 23:52:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=5KKgUz5YyNrIVW2I2F3VaFQYKRHQzw+f6Q47JuBNb0I=; b=01ccH/uDSRq2940uIB2lUNLp3VtzsLkTDZ0vPGsobSEP8fMMV16lUPdNemIowkwQzh ql5RnhgWtZubiRrL5FBK9+S+aaZk5e8YAZ8wn3nDoNR7yqrAUhj/sXcTjJc85dCmG+Ld ttEyMHg62+YStjR2BGjKwBkl/Pll9w0R85lv7aMFqQzkDcZcN9cvryxaPwAXx76Wn0IZ gHeqYixld8Lz5FtG+hTocxCFoMOrtt0rhO8CvqO8MeQg9HCfUWe1XXuXIC4BAv0BjX47 Gn4FdDX0xAiVrRjb9fy64edwN5RvRwm+tUI64i8TFawsv/nNavMJDEvvGA++l+LP3oCz c5Pg== X-Received: by 10.66.161.136 with SMTP id xs8mr1041870pab.144.1361346776616; Tue, 19 Feb 2013 23:52:56 -0800 (PST) Received: from anchor.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id c8sm20826347pbq.10.2013.02.19.23.52.54 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 19 Feb 2013 23:52:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Feb 2013 23:52:01 -0800 Message-Id: <1361346746-8511-14-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1361346746-8511-1-git-send-email-rth@twiddle.net> References: <1361346746-8511-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.160.50 Cc: blauwirbel@gmail.com, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 13/38] tcg: Implement muls2 with mulu2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index dac3b4e..d70b2eb 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2396,6 +2396,26 @@ static inline void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2); /* Allow the optimizer room to replace muls2 with two moves. */ tcg_gen_op0(INDEX_op_nop); + } else if (TCG_TARGET_REG_BITS == 32 && TCG_TARGET_HAS_mulu2_i32) { + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + tcg_gen_op4_i32(INDEX_op_mulu2_i32, t0, t1, arg1, arg2); + /* Allow the optimizer room to replace mulu2 with two moves. */ + tcg_gen_op0(INDEX_op_nop); + /* Adjust for negative inputs. */ + tcg_gen_sari_i32(t2, arg1, 31); + tcg_gen_sari_i32(t3, arg2, 31); + tcg_gen_and_i32(t2, t2, arg2); + tcg_gen_and_i32(t3, t3, arg1); + tcg_gen_sub_i32(rh, t1, t2); + tcg_gen_sub_i32(rh, rh, t3); + tcg_gen_mov_i32(rl, t0); + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); } else { TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t1 = tcg_temp_new_i64(); @@ -2455,6 +2475,26 @@ static inline void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, tcg_gen_op4_i64(INDEX_op_mulu2_i64, rl, rh, arg1, arg2); /* Allow the optimizer room to replace mulu2 with two moves. */ tcg_gen_op0(INDEX_op_nop); + } else if (TCG_TARGET_HAS_mulu2_i64) { + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + tcg_gen_op4_i64(INDEX_op_mulu2_i64, t0, t1, arg1, arg2); + /* Allow the optimizer room to replace mulu2 with two moves. */ + tcg_gen_op0(INDEX_op_nop); + /* Adjust for negative inputs. */ + tcg_gen_sari_i64(t2, arg1, 63); + tcg_gen_sari_i64(t3, arg2, 63); + tcg_gen_and_i64(t2, t2, arg2); + tcg_gen_and_i64(t3, t3, arg1); + tcg_gen_sub_i64(rh, t1, t2); + tcg_gen_sub_i64(rh, rh, t3); + tcg_gen_mov_i64(rl, t0); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + tcg_temp_free_i64(t3); } else { TCGv_i64 t0 = tcg_temp_new_i64(); int sizemask = 0;