Patchwork [27/38] target-ppc: Compute addition overflow without branches

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Submitter Richard Henderson
Date Feb. 20, 2013, 7:52 a.m.
Message ID <1361346746-8511-28-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/222017/
State New
Headers show

Comments

Richard Henderson - Feb. 20, 2013, 7:52 a.m.
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-ppc/translate.c | 46 +++++++++++++---------------------------------
 1 file changed, 13 insertions(+), 33 deletions(-)

Patch

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7aab6ae..116cf12 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -746,35 +746,23 @@  static void gen_isel(DisasContext *ctx)
 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
                                            TCGv arg1, TCGv arg2, int sub)
 {
-    int l1;
-    TCGv t0;
+    TCGv t0 = tcg_temp_new();
 
-    l1 = gen_new_label();
-    /* Start with XER OV disabled, the most likely case */
-    tcg_gen_movi_tl(cpu_ov, 0);
-    t0 = tcg_temp_local_new();
-    tcg_gen_xor_tl(t0, arg0, arg1);
-#if defined(TARGET_PPC64)
-    if (!ctx->sf_mode)
-        tcg_gen_ext32s_tl(t0, t0);
-#endif
-    if (sub)
-        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
-    else
-        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
+    tcg_gen_xor_tl(cpu_ov, arg0, arg1);
     tcg_gen_xor_tl(t0, arg1, arg2);
+    if (sub) {
+        tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
+    } else {
+        tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
+    }
+    tcg_temp_free(t0);
 #if defined(TARGET_PPC64)
-    if (!ctx->sf_mode)
-        tcg_gen_ext32s_tl(t0, t0);
+    if (!ctx->sf_mode) {
+        tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
+    }
 #endif
-    if (sub)
-        tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
-    else
-        tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
-    tcg_gen_movi_tl(cpu_ov, 1);
-    tcg_gen_movi_tl(cpu_so, 1);
-    gen_set_label(l1);
-    tcg_temp_free(t0);
+    tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
+    tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
 }
 
 static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
@@ -837,10 +825,6 @@  static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
         /* Start with XER CA disabled, the most likely case */
         tcg_gen_movi_tl(cpu_ca, 0);
     }
-    if (compute_ov) {
-        /* Start with XER OV disabled, the most likely case */
-        tcg_gen_movi_tl(cpu_ov, 0);
-    }
 
     tcg_gen_add_tl(t0, arg1, arg2);
 
@@ -1261,10 +1245,6 @@  static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
         /* Start with XER CA disabled, the most likely case */
         tcg_gen_movi_tl(cpu_ca, 0);
     }
-    if (compute_ov) {
-        /* Start with XER OV disabled, the most likely case */
-        tcg_gen_movi_tl(cpu_ov, 0);
-    }
 
     if (add_ca) {
         tcg_gen_not_tl(t0, arg1);