From patchwork Wed Feb 20 07:52:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 222008 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DE3A22C0082 for ; Wed, 20 Feb 2013 20:05:41 +1100 (EST) Received: from localhost ([::1]:34157 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U85cS-0003Gt-12 for incoming@patchwork.ozlabs.org; Wed, 20 Feb 2013 04:05:40 -0500 Received: from eggs.gnu.org ([208.118.235.92]:43861) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U84UR-0001m0-Vx for qemu-devel@nongnu.org; Wed, 20 Feb 2013 02:53:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U84UO-0002GX-Ua for qemu-devel@nongnu.org; Wed, 20 Feb 2013 02:53:19 -0500 Received: from mail-da0-f49.google.com ([209.85.210.49]:52494) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U84UN-0002FR-Ie for qemu-devel@nongnu.org; Wed, 20 Feb 2013 02:53:16 -0500 Received: by mail-da0-f49.google.com with SMTP id t11so3420886daj.36 for ; Tue, 19 Feb 2013 23:53:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=vo034OTKPcDQCt7YTXOA/YpK25CdSW4LNaThR60VK3I=; b=AdaMg+HRd2mbdn3palHTTOUe3FHBOX2LNFOrVmHeE8d07qufkvTeKMNmUnAl2WrcyK uoqFAXo3BppThDWGe0EVKeF/wUhc+VkA3/ngnylTkupheO4pioeZhI+/EI78gs9Nrgyn Kk0tyMsZf5m0XYUp2mtzVbncAvyZB1ktbP/FGrVOVBNEOKf4rPBO9Rd6Dy/oaN5uB5zh 9XSPY4WzfAVntWz399EsT/PIbbdU8ids0DX8PlzAcdzpMFZ/pyKRnZh5RN4cO6pq4ny7 GjhAUVsbkWjV8DrhG39AGp01Dzx+PV/55PJUXeAEpAucwBxe63t0PwciEZulm5r/nMgz rLHw== X-Received: by 10.66.4.37 with SMTP id h5mr1017108pah.210.1361346789654; Tue, 19 Feb 2013 23:53:09 -0800 (PST) Received: from anchor.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id c8sm20826347pbq.10.2013.02.19.23.53.07 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 19 Feb 2013 23:53:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Feb 2013 23:52:08 -0800 Message-Id: <1361346746-8511-21-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1361346746-8511-1-git-send-email-rth@twiddle.net> References: <1361346746-8511-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.210.49 Cc: blauwirbel@gmail.com, Peter Maydell , aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 20/38] target-arm: Implement adc_cc inline X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use add2 if available, otherwise use 64-bit arithmetic. Cc: Peter Maydell Signed-off-by: Richard Henderson --- target-arm/helper.h | 1 - target-arm/op_helper.c | 15 --------------- target-arm/translate.c | 39 ++++++++++++++++++++++++++++++++++----- 3 files changed, 34 insertions(+), 21 deletions(-) diff --git a/target-arm/helper.h b/target-arm/helper.h index bca5a5b..507bb9c 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -140,7 +140,6 @@ DEF_HELPER_2(recpe_u32, i32, i32, env) DEF_HELPER_2(rsqrte_u32, i32, i32, env) DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32) -DEF_HELPER_3(adc_cc, i32, env, i32, i32) DEF_HELPER_3(sbc_cc, i32, env, i32, i32) DEF_HELPER_3(shl_cc, i32, env, i32, i32) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 99610d7..49fc036 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -315,21 +315,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) The only way to do that in TCG is a conditional branch, which clobbers all our temporaries. For now implement these as helper functions. */ -uint32_t HELPER(adc_cc)(CPUARMState *env, uint32_t a, uint32_t b) -{ - uint32_t result; - if (!env->CF) { - result = a + b; - env->CF = result < a; - } else { - result = a + b + 1; - env->CF = result <= a; - } - env->VF = (a ^ b ^ -1) & (a ^ result); - env->NF = env->ZF = result; - return result; -} - uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b) { uint32_t result; diff --git a/target-arm/translate.c b/target-arm/translate.c index ca6f0af..493448a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -421,6 +421,34 @@ static void gen_add_CC(TCGv dest, TCGv t0, TCGv t1) tcg_gen_mov_i32(dest, cpu_NF); } +/* dest = T0 + T1 + CF. Compute C, N, V and Z flags */ +static void gen_adc_CC(TCGv dest, TCGv t0, TCGv t1) +{ + TCGv tmp = tcg_temp_new_i32(); + if (TCG_TARGET_HAS_add2_i32) { + tcg_gen_movi_i32(tmp, 0); + tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp); + tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, cpu_CF, t1, tmp); + } else { + TCGv_i64 q0 = tcg_temp_new_i64(); + TCGv_i64 q1 = tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(q0, t0); + tcg_gen_extu_i32_i64(q1, t1); + tcg_gen_add_i64(q0, q0, q1); + tcg_gen_extu_i32_i64(q1, cpu_CF); + tcg_gen_add_i64(q0, q0, q1); + tcg_gen_extr_i64_i32(cpu_NF, cpu_CF, q0); + tcg_temp_free_i64(q0); + tcg_temp_free_i64(q1); + } + tcg_gen_mov_i32(cpu_ZF, cpu_NF); + tcg_gen_xor_i32(cpu_VF, cpu_NF, t0); + tcg_gen_xor_i32(tmp, t0, t1); + tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); + tcg_temp_free_i32(tmp); + tcg_gen_mov_i32(dest, cpu_NF); +} + /* dest = T0 - T1. Compute C, N, V and Z flags */ static void gen_sub_CC(TCGv dest, TCGv t0, TCGv t1) { @@ -7073,7 +7101,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) break; case 0x05: if (set_cc) { - gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2); + gen_adc_CC(tmp, tmp, tmp2); } else { gen_add_carry(tmp, tmp, tmp2); } @@ -7914,7 +7942,7 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCG break; case 10: /* adc */ if (conds) - gen_helper_adc_cc(t0, cpu_env, t0, t1); + gen_adc_CC(t0, t0, t1); else gen_adc(t0, t1); break; @@ -9232,10 +9260,11 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) } break; case 0x5: /* adc */ - if (s->condexec_mask) + if (s->condexec_mask) { gen_adc(tmp, tmp2); - else - gen_helper_adc_cc(tmp, cpu_env, tmp, tmp2); + } else { + gen_adc_CC(tmp, tmp, tmp2); + } break; case 0x6: /* sbc */ if (s->condexec_mask)