From patchwork Tue Feb 19 17:39:38 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 221921 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 833052C0086 for ; Wed, 20 Feb 2013 10:48:10 +1100 (EST) Received: from localhost ([::1]:35681 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U7rBx-0005XS-Iw for incoming@patchwork.ozlabs.org; Tue, 19 Feb 2013 12:41:21 -0500 Received: from eggs.gnu.org ([208.118.235.92]:43938) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U7rBX-0004tl-0m for qemu-devel@nongnu.org; Tue, 19 Feb 2013 12:41:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U7rBN-0007sU-E6 for qemu-devel@nongnu.org; Tue, 19 Feb 2013 12:40:54 -0500 Received: from mail-pa0-f43.google.com ([209.85.220.43]:43520) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U7rBM-0007s5-L6 for qemu-devel@nongnu.org; Tue, 19 Feb 2013 12:40:44 -0500 Received: by mail-pa0-f43.google.com with SMTP id bh2so3491259pad.2 for ; Tue, 19 Feb 2013 09:40:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=l5Fe0Jkrh+AeghCjpp+qk5iA+oC7/hnFiJyd2PpD/6k=; b=DKLtBCDKjnEE12ri6Rb2thmnIp1dMUDwSXOAPIWSAzp//XdGN9Z4Ay4VGfgsza0+w5 FMVM8gRvcRDwvNKPrEvJmREjKnb2sHOQV4I60ikm1S7iV7wYWELYVf2U+KP9vN6niWrN HdyjC8wKf2MMzpCSTDOFLldPCBERvXdrzFdHRaydQuuqtXREvRobYq7/+70S1lyLLYZh Zh/0l8zeh91kS+s3v/v/NjDaVPV1LaKB3Wl+MFl7iNwsb+41zWx78fdsNIkvIcohfRdd atxUQZPM4XwbyFK811Fds7xo/667KbUIOux0OGiou7KMVb3OX77AVd4/XVFOj4UeWQXS o+rQ== X-Received: by 10.68.204.164 with SMTP id kz4mr41996306pbc.158.1361295643955; Tue, 19 Feb 2013 09:40:43 -0800 (PST) Received: from anchor.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id 1sm18659295pbg.18.2013.02.19.09.40.41 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 19 Feb 2013 09:40:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 19 Feb 2013 09:39:38 -0800 Message-Id: <1361295631-21316-5-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1361295631-21316-1-git-send-email-rth@twiddle.net> References: <1361295631-21316-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.220.43 Cc: blauwirbel@gmail.com, pbonzini@redhat.com, afaerber@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 04/57] target-i386: introduce gen_ext_tl X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Paolo Bonzini Introduce a function that abstracts extracting an 8, 16, 32 or 64-bit value with or without sign, generalizing gen_extu and gen_exts. Reviewed-by: Blue Swirl Signed-off-by: Paolo Bonzini Signed-off-by: Richard Henderson --- target-i386/translate.c | 146 ++++++++++++------------------------------------ 1 file changed, 37 insertions(+), 109 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 94e1434..ccb06e2 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -659,38 +659,45 @@ static inline void gen_op_movl_T0_Dshift(int ot) tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot); }; -static void gen_extu(int ot, TCGv reg) +static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign) { - switch(ot) { + switch (size) { case OT_BYTE: - tcg_gen_ext8u_tl(reg, reg); - break; + if (sign) { + tcg_gen_ext8s_tl(dst, src); + } else { + tcg_gen_ext8u_tl(dst, src); + } + return dst; case OT_WORD: - tcg_gen_ext16u_tl(reg, reg); - break; + if (sign) { + tcg_gen_ext16s_tl(dst, src); + } else { + tcg_gen_ext16u_tl(dst, src); + } + return dst; +#ifdef TARGET_X86_64 case OT_LONG: - tcg_gen_ext32u_tl(reg, reg); - break; + if (sign) { + tcg_gen_ext32s_tl(dst, src); + } else { + tcg_gen_ext32u_tl(dst, src); + } + return dst; +#endif default: - break; + return src; } } +static void gen_extu(int ot, TCGv reg) +{ + gen_ext_tl(reg, reg, ot, false); +} + static void gen_exts(int ot, TCGv reg) { - switch(ot) { - case OT_BYTE: - tcg_gen_ext8s_tl(reg, reg); - break; - case OT_WORD: - tcg_gen_ext16s_tl(reg, reg); - break; - case OT_LONG: - tcg_gen_ext32s_tl(reg, reg); - break; - default: - break; - } + gen_ext_tl(reg, reg, ot, true); } static inline void gen_op_jnz_ecx(int size, int label1) @@ -966,54 +973,15 @@ static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1) switch(jcc_op) { case JCC_Z: fast_jcc_z: - switch(size) { - case 0: - tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff); - t0 = cpu_tmp0; - break; - case 1: - tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff); - t0 = cpu_tmp0; - break; -#ifdef TARGET_X86_64 - case 2: - tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff); - t0 = cpu_tmp0; - break; -#endif - default: - t0 = cpu_cc_dst; - break; - } + t0 = gen_ext_tl(cpu_tmp0, cpu_cc_dst, size, false); tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1); break; case JCC_S: fast_jcc_s: - switch(size) { - case 0: - tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80); - tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, - 0, l1); - break; - case 1: - tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000); - tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, - 0, l1); - break; -#ifdef TARGET_X86_64 - case 2: - tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000); - tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, - 0, l1); - break; -#endif - default: - tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, - 0, l1); - break; - } + t0 = gen_ext_tl(cpu_tmp0, cpu_cc_dst, size, true); + tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, t0, 0, l1); break; - + case JCC_B: cond = inv ? TCG_COND_GEU : TCG_COND_LTU; goto fast_jcc_b; @@ -1021,28 +989,8 @@ static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1) cond = inv ? TCG_COND_GTU : TCG_COND_LEU; fast_jcc_b: tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); - switch(size) { - case 0: - t0 = cpu_tmp0; - tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff); - tcg_gen_andi_tl(t0, cpu_cc_src, 0xff); - break; - case 1: - t0 = cpu_tmp0; - tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff); - tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff); - break; -#ifdef TARGET_X86_64 - case 2: - t0 = cpu_tmp0; - tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff); - tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff); - break; -#endif - default: - t0 = cpu_cc_src; - break; - } + gen_extu(size, cpu_tmp4); + t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false); tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); break; @@ -1053,28 +1001,8 @@ static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1) cond = inv ? TCG_COND_GT : TCG_COND_LE; fast_jcc_l: tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src); - switch(size) { - case 0: - t0 = cpu_tmp0; - tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4); - tcg_gen_ext8s_tl(t0, cpu_cc_src); - break; - case 1: - t0 = cpu_tmp0; - tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4); - tcg_gen_ext16s_tl(t0, cpu_cc_src); - break; -#ifdef TARGET_X86_64 - case 2: - t0 = cpu_tmp0; - tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4); - tcg_gen_ext32s_tl(t0, cpu_cc_src); - break; -#endif - default: - t0 = cpu_cc_src; - break; - } + gen_exts(size, cpu_tmp4); + t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true); tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); break;