Patchwork [U-Boot,v2,01/11] Blackfin: bf60x: new processor header files

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Submitter Sonic Zhang
Date Feb. 19, 2013, 7 a.m.
Message ID <1361257266-3722-2-git-send-email-sonic.adi@gmail.com>
Download mbox | patch
Permalink /patch/221638/
State Superseded
Delegated to: Tom Rini
Headers show

Comments

Sonic Zhang - Feb. 19, 2013, 7 a.m.
From: Bob Liu <lliubbo@gmail.com>

Add header files for blackfin new processor bf60x.

Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
---
 arch/blackfin/include/asm/blackfin_cdef.h         |    3 +
 arch/blackfin/include/asm/blackfin_def.h          |    5 +
 arch/blackfin/include/asm/blackfin_local.h        |    3 +
 arch/blackfin/include/asm/mach-bf609/BF609_cdef.h |  551 +++
 arch/blackfin/include/asm/mach-bf609/BF609_def.h  | 3758 +++++++++++++++++++++
 arch/blackfin/include/asm/mach-bf609/anomaly.h    |  103 +
 arch/blackfin/include/asm/mach-bf609/def_local.h  |    5 +
 arch/blackfin/include/asm/mach-bf609/portmux.h    |  257 ++
 arch/blackfin/include/asm/mach-bf609/ports.h      |  103 +
 arch/blackfin/include/asm/mach-common/bits/cgu.h  |   80 +
 arch/blackfin/include/asm/mach-common/bits/dde.h  |   88 +
 arch/blackfin/include/asm/mach-common/bits/mpu.h  |    6 +-
 arch/blackfin/include/asm/mach-common/bits/pll.h  |    5 +
 13 files changed, 4966 insertions(+), 1 deletions(-)
 create mode 100644 arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
 create mode 100644 arch/blackfin/include/asm/mach-bf609/BF609_def.h
 create mode 100644 arch/blackfin/include/asm/mach-bf609/anomaly.h
 create mode 100644 arch/blackfin/include/asm/mach-bf609/def_local.h
 create mode 100644 arch/blackfin/include/asm/mach-bf609/portmux.h
 create mode 100644 arch/blackfin/include/asm/mach-bf609/ports.h
 create mode 100644 arch/blackfin/include/asm/mach-common/bits/cgu.h
 create mode 100644 arch/blackfin/include/asm/mach-common/bits/dde.h
Wolfgang Denk - Feb. 19, 2013, 10:15 a.m.
Dear Sonic Zhang,

In message <1361257266-3722-2-git-send-email-sonic.adi@gmail.com> you wrote:
> 
> Add header files for blackfin new processor bf60x.
...
>  arch/blackfin/include/asm/mach-bf609/BF609_def.h  | 3758 +++++++++++++++++++++

This is a bit excessive, isn't it?  Do we really all thse many
thousands lines of defines?


> diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
> new file mode 100644
> index 0000000..39b740f
> --- /dev/null
> +++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
> @@ -0,0 +1,3758 @@
> +/* DO NOT EDIT THIS FILE
> + * Automatically generated by generate-def-headers.xsl
> + * DO NOT EDIT THIS FILE
> + */
> +
> +#ifndef __BFIN_DEF_ADSP_BF609_proc__
> +#define __BFIN_DEF_ADSP_BF609_proc__
> +
> +#include "../mach-common/ADSP-EDN-core_def.h"
> +
> +#define CNT_CFG                     0xFFC00400         /* CNT0 Configuration Register */
> +#define CNT_IMSK                    0xFFC00404         /* CNT0 Interrupt Mask Register */
> +#define CNT_STAT                    0xFFC00408         /* CNT0 Status Register */
> +#define CNT_CMD                     0xFFC0040C         /* CNT0 Command Register */
> +#define CNT_DEBNCE                  0xFFC00410         /* CNT0 Debounce Register */
> +#define CNT_CNTR                    0xFFC00414         /* CNT0 Counter Register */
> +#define CNT_MAX                     0xFFC00418         /* CNT0 Maximum Count Register */
> +#define CNT_MIN                     0xFFC0041C         /* CNT0 Minimum Count Register */
> +
> +#define RSI_CLK_CONTROL             0xFFC00604         /* RSI0 Clock Control Register */
> +#define RSI_ARGUMENT                0xFFC00608         /* RSI0 Argument Register */
> +#define RSI_COMMAND                 0xFFC0060C         /* RSI0 Command Register */
> +#define RSI_RESP_CMD                0xFFC00610         /* RSI0 Response Command Register */
> +#define RSI_RESPONSE0               0xFFC00614         /* RSI0 Response 0 Register */
> +#define RSI_RESPONSE1               0xFFC00618         /* RSI0 Response 1 Register */
> +#define RSI_RESPONSE2               0xFFC0061C         /* RSI0 Response 2 Register */
> +#define RSI_RESPONSE3               0xFFC00620         /* RSI0 Response 3 Register */
> +#define RSI_DATA_TIMER              0xFFC00624         /* RSI0 Data Timer Register */
> +#define RSI_DATA_LGTH               0xFFC00628         /* RSI0 Data Length Register */
> +#define RSI_DATA_CONTROL            0xFFC0062C         /* RSI0 Data Control Register */
> +#define RSI_DATA_CNT                0xFFC00630         /* RSI0 Data Count Register */
> +#define RSI_STATUS                  0xFFC00634         /* RSI0 Status Register */
> +#define RSI_STATUSCL                0xFFC00638         /* RSI0 Status Clear Register */
> +#define RSI_IMSK0                   0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
> +#define RSI_IMSK1                   0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
> +#define RSI_FIFO_CNT                0xFFC00648         /* RSI0 FIFO Counter Register */
...

I think I mentioned before that device registers have to be described
using C structs in U-Boot, and proper I/O accessors must be used to
access these.

In any case, please trim to the really needed definitions.

> --- /dev/null
> +++ b/arch/blackfin/include/asm/mach-bf609/anomaly.h
> @@ -0,0 +1,103 @@
> +/*
> + * DO NOT EDIT THIS FILE
> + * This file is under version control at
> + *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
> + * and can be replaced with that version at any time
> + * DO NOT EDIT THIS FILE

This makes no sense to me.

> + * Copyright 2004-2012 Analog Devices Inc.
> + * Licensed under the ADI BSD license.
> + *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
> + */

I'm not sure if this has been discussed before - is this really GPL
compatible?



Best regards,

Wolfgang Denk
Sonic Zhang - Feb. 20, 2013, 3:20 a.m.
Hi Wolfgang,


On Tue, Feb 19, 2013 at 6:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Sonic Zhang,
>
> In message <1361257266-3722-2-git-send-email-sonic.adi@gmail.com> you wrote:
>>
>> Add header files for blackfin new processor bf60x.
> ...
>>  arch/blackfin/include/asm/mach-bf609/BF609_def.h  | 3758 +++++++++++++++++++++
>
> This is a bit excessive, isn't it?  Do we really all thse many
> thousands lines of defines?
>
>
>> diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
>> new file mode 100644
>> index 0000000..39b740f
>> --- /dev/null
>> +++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
>> @@ -0,0 +1,3758 @@
>> +/* DO NOT EDIT THIS FILE
>> + * Automatically generated by generate-def-headers.xsl
>> + * DO NOT EDIT THIS FILE
>> + */
>> +
>> +#ifndef __BFIN_DEF_ADSP_BF609_proc__
>> +#define __BFIN_DEF_ADSP_BF609_proc__
>> +
>> +#include "../mach-common/ADSP-EDN-core_def.h"
>> +
>> +#define CNT_CFG                     0xFFC00400         /* CNT0 Configuration Register */
>> +#define CNT_IMSK                    0xFFC00404         /* CNT0 Interrupt Mask Register */
>> +#define CNT_STAT                    0xFFC00408         /* CNT0 Status Register */
>> +#define CNT_CMD                     0xFFC0040C         /* CNT0 Command Register */
>> +#define CNT_DEBNCE                  0xFFC00410         /* CNT0 Debounce Register */
>> +#define CNT_CNTR                    0xFFC00414         /* CNT0 Counter Register */
>> +#define CNT_MAX                     0xFFC00418         /* CNT0 Maximum Count Register */
>> +#define CNT_MIN                     0xFFC0041C         /* CNT0 Minimum Count Register */
>> +
>> +#define RSI_CLK_CONTROL             0xFFC00604         /* RSI0 Clock Control Register */
>> +#define RSI_ARGUMENT                0xFFC00608         /* RSI0 Argument Register */
>> +#define RSI_COMMAND                 0xFFC0060C         /* RSI0 Command Register */
>> +#define RSI_RESP_CMD                0xFFC00610         /* RSI0 Response Command Register */
>> +#define RSI_RESPONSE0               0xFFC00614         /* RSI0 Response 0 Register */
>> +#define RSI_RESPONSE1               0xFFC00618         /* RSI0 Response 1 Register */
>> +#define RSI_RESPONSE2               0xFFC0061C         /* RSI0 Response 2 Register */
>> +#define RSI_RESPONSE3               0xFFC00620         /* RSI0 Response 3 Register */
>> +#define RSI_DATA_TIMER              0xFFC00624         /* RSI0 Data Timer Register */
>> +#define RSI_DATA_LGTH               0xFFC00628         /* RSI0 Data Length Register */
>> +#define RSI_DATA_CONTROL            0xFFC0062C         /* RSI0 Data Control Register */
>> +#define RSI_DATA_CNT                0xFFC00630         /* RSI0 Data Count Register */
>> +#define RSI_STATUS                  0xFFC00634         /* RSI0 Status Register */
>> +#define RSI_STATUSCL                0xFFC00638         /* RSI0 Status Clear Register */
>> +#define RSI_IMSK0                   0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
>> +#define RSI_IMSK1                   0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
>> +#define RSI_FIFO_CNT                0xFFC00648         /* RSI0 FIFO Counter Register */
> ...
>
> I think I mentioned before that device registers have to be described
> using C structs in U-Boot, and proper I/O accessors must be used to
> access these.
>
> In any case, please trim to the really needed definitions.

OK. I will trim the head file to those that are really used in drivers.

>
>> --- /dev/null
>> +++ b/arch/blackfin/include/asm/mach-bf609/anomaly.h
>> @@ -0,0 +1,103 @@
>> +/*
>> + * DO NOT EDIT THIS FILE
>> + * This file is under version control at
>> + *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
>> + * and can be replaced with that version at any time
>> + * DO NOT EDIT THIS FILE
>
> This makes no sense to me.

OK, I will remove these lines.

>
>> + * Copyright 2004-2012 Analog Devices Inc.
>> + * Licensed under the ADI BSD license.
>> + *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
>> + */
>
> I'm not sure if this has been discussed before - is this really GPL
> compatible?
>

The adi_bsd license comment is the same as those in the head files for
BF5xx, which were already merged in to the U-boot mainline git tree.
As the document says "The ADI BSD License is similar to the Clear BSD
License, which the Free Software Foundation indicates is compatible
with both GPLv2 and GPLv3."

I think this has already been discussed when Mike Frysinger got the
Blackfin architecture code merged upstream.


Regards,

Sonic

>
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
> Harrison's Postulate:
>         For every action, there is an equal and opposite criticism.

Patch

diff --git a/arch/blackfin/include/asm/blackfin_cdef.h b/arch/blackfin/include/asm/blackfin_cdef.h
index a19f0f7..8608711 100644
--- a/arch/blackfin/include/asm/blackfin_cdef.h
+++ b/arch/blackfin/include/asm/blackfin_cdef.h
@@ -84,5 +84,8 @@ 
 #ifdef __ADSPBF561__
 # include "mach-bf561/BF561_cdef.h"
 #endif
+#ifdef __ADSPBF609__
+# include "mach-bf609/BF609_cdef.h"
+#endif
 
 #endif /* __MACH_CDEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_def.h b/arch/blackfin/include/asm/blackfin_def.h
index f06d1f1..c96a3ec 100644
--- a/arch/blackfin/include/asm/blackfin_def.h
+++ b/arch/blackfin/include/asm/blackfin_def.h
@@ -136,5 +136,10 @@ 
 # include "mach-bf561/anomaly.h"
 # include "mach-bf561/def_local.h"
 #endif
+#ifdef __ADSPBF609__
+# include "mach-bf609/BF609_def.h"
+# include "mach-bf609/anomaly.h"
+# include "mach-bf609/def_local.h"
+#endif
 
 #endif /* __MACH_DEF_BLACKFIN__ */
diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h
index 49d0c9e..fc46ef4 100644
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -61,6 +61,9 @@ 
 extern u_long get_vco(void);
 extern u_long get_cclk(void);
 extern u_long get_sclk(void);
+extern u_long get_sclk0(void);
+extern u_long get_sclk1(void);
+extern u_long get_dclk(void);
 
 # define bfin_revid() (bfin_read_CHIPID() >> 28)
 
diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h b/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
new file mode 100644
index 0000000..848c79c
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/BF609_cdef.h
@@ -0,0 +1,551 @@ 
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF609_proc__
+#define __BFIN_CDEF_ADSP_BF609_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#define bfin_read_CGU_STAT() bfin_read32(CGU_STAT)
+#define bfin_read_CGU_CLKOUTSEL() bfin_read32(CGU_CLKOUTSEL)
+#define bfin_read_CGU_CTL() bfin_read32(CGU_CTL)
+#define bfin_write_CGU_CTL(val) bfin_write32(CGU_CTL, val)
+#define bfin_read_CGU_DIV() bfin_read32(CGU_DIV)
+#define bfin_write_CGU_DIV(val) bfin_write32(CGU_DIV, val)
+
+#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
+#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
+
+#define bfin_read_CHIPID()		bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)		bfin_write32(CHIPID, val)
+
+#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
+#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
+#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
+#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
+#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
+#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
+#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
+#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
+#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
+#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
+#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
+#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
+#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
+#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
+#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
+#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
+#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
+#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
+
+#define bfin_read_SEC_CCTL()		bfin_read32(SEC0_CCTL0)
+#define bfin_write_SEC_CCTL(val)	bfin_write32(SEC0_CCTL0, val)
+#define bfin_read_SEC_GCTL()		bfin_read32(SEC0_GCTL)
+#define bfin_write_SEC_GCTL(val)	bfin_write32(SEC0_GCTL, val)
+
+#define bfin_read_SEC_FCTL()		bfin_read32(SEC0_FCTL)
+#define bfin_write_SEC_FCTL(val)	bfin_write32(SEC0_FCTL, val)
+#define bfin_read_SEC_SCTL(sid)		bfin_read32((SEC0_SCTL0 + (sid) * 8))
+#define bfin_write_SEC_SCTL(sid, val)	bfin_write32((SEC0_SCTL0 + (sid) * 8), val)
+
+#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
+#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
+#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
+#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
+#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
+#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
+#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
+#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
+#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
+#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
+#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
+#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
+#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
+#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
+#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
+#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
+#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
+#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
+#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
+#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
+#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
+#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
+#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
+#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
+#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
+#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
+#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
+
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLL_OSC)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
+#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
+#define bfin_read_USB_DMA_INTERRUPT()  bfin_read8(USB_DMA_IRQ)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write8(USB_DMA_IRQ, val)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
+#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
+
+#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_DSCPTR_NXT)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_DSCPTR_NXT, val)
+#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_ADDRSTART)
+#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_ADDRSTART, val)
+#define bfin_read_DMA0_CONFIG() bfin_read32(DMA0_CFG)
+#define bfin_write_DMA0_CONFIG(val) bfin_write32(DMA0_CFG, val)
+#define bfin_read_DMA0_X_COUNT() bfin_read32(DMA0_XCNT)
+#define bfin_write_DMA0_X_COUNT(val) bfin_write32(DMA0_XCNT, val)
+#define bfin_read_DMA0_X_MODIFY() bfin_read32(DMA0_XMOD)
+#define bfin_write_DMA0_X_MODIFY(val) bfin_write32(DMA0_XMOD, val)
+#define bfin_read_DMA0_Y_COUNT() bfin_read32(DMA0_YCNT)
+#define bfin_write_DMA0_Y_COUNT(val) bfin_write32(DMA0_YCNT, val)
+#define bfin_read_DMA0_Y_MODIFY() bfin_read32(DMA0_YMOD)
+#define bfin_write_DMA0_Y_MODIFY(val) bfin_write32(DMA0_YMOD, val)
+#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_DSCPTR_CUR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_DSCPTR_CUR, val)
+#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_ADDR_CUR)
+#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_ADDR_CUR, val)
+#define bfin_read_DMA0_IRQ_STATUS() bfin_read32(DMA0_STAT)
+#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write32(DMA0_STAT, val)
+#define bfin_read_DMA0_CURR_X_COUNT() bfin_read32(DMA0_XCNT_CUR)
+#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write32(DMA0_XCNT_CUR, val)
+#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read32(DMA0_YCNT_CUR)
+#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write32(DMA0_YCNT_CUR, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_DSCPTR_NXT)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_DSCPTR_NXT, val)
+#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_ADDRSTART)
+#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_ADDRSTART, val)
+#define bfin_read_DMA1_CONFIG() bfin_read32(DMA1_CFG)
+#define bfin_write_DMA1_CONFIG(val) bfin_write32(DMA1_CFG, val)
+#define bfin_read_DMA1_X_COUNT() bfin_read32(DMA1_XCNT)
+#define bfin_write_DMA1_X_COUNT(val) bfin_write32(DMA1_XCNT, val)
+#define bfin_read_DMA1_X_MODIFY() bfin_read32(DMA1_XMOD)
+#define bfin_write_DMA1_X_MODIFY(val) bfin_write32(DMA1_XMOD, val)
+#define bfin_read_DMA1_Y_COUNT() bfin_read32(DMA1_YCNT)
+#define bfin_write_DMA1_Y_COUNT(val) bfin_write32(DMA1_YCNT, val)
+#define bfin_read_DMA1_Y_MODIFY() bfin_read32(DMA1_YMOD)
+#define bfin_write_DMA1_Y_MODIFY(val) bfin_write32(DMA1_YMOD, val)
+#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_DSCPTR_CUR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_DSCPTR_CUR, val)
+#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_ADDR_CUR)
+#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_ADDR_CUR, val)
+#define bfin_read_DMA1_IRQ_STATUS() bfin_read32(DMA1_STAT)
+#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write32(DMA1_STAT, val)
+#define bfin_read_DMA1_CURR_X_COUNT() bfin_read32(DMA1_XCNT_CUR)
+#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write32(DMA1_XCNT_CUR, val)
+#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read32(DMA1_YCNT_CUR)
+#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write32(DMA1_YCNT_CUR, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_DSCPTR_NXT)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_DSCPTR_NXT, val)
+#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_ADDRSTART)
+#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_ADDRSTART, val)
+#define bfin_read_DMA2_CONFIG() bfin_read32(DMA2_CFG)
+#define bfin_write_DMA2_CONFIG(val) bfin_write32(DMA2_CFG, val)
+#define bfin_read_DMA2_X_COUNT() bfin_read32(DMA2_XCNT)
+#define bfin_write_DMA2_X_COUNT(val) bfin_write32(DMA2_XCNT, val)
+#define bfin_read_DMA2_X_MODIFY() bfin_read32(DMA2_XMOD)
+#define bfin_write_DMA2_X_MODIFY(val) bfin_write32(DMA2_XMOD, val)
+#define bfin_read_DMA2_Y_COUNT() bfin_read32(DMA2_YCNT)
+#define bfin_write_DMA2_Y_COUNT(val) bfin_write32(DMA2_YCNT, val)
+#define bfin_read_DMA2_Y_MODIFY() bfin_read32(DMA2_YMOD)
+#define bfin_write_DMA2_Y_MODIFY(val) bfin_write32(DMA2_YMOD, val)
+#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_DSCPTR_CUR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_DSCPTR_CUR, val)
+#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_ADDR_CUR)
+#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_ADDR_CUR, val)
+#define bfin_read_DMA2_IRQ_STATUS() bfin_read32(DMA2_STAT)
+#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write32(DMA2_STAT, val)
+#define bfin_read_DMA2_CURR_X_COUNT() bfin_read32(DMA2_XCNT_CUR)
+#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write32(DMA2_XCNT_CUR, val)
+#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read32(DMA2_YCNT_CUR)
+#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write32(DMA2_YCNT_CUR, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_DSCPTR_NXT)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_DSCPTR_NXT, val)
+#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_ADDRSTART)
+#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_ADDRSTART, val)
+#define bfin_read_DMA3_CONFIG() bfin_read32(DMA3_CFG)
+#define bfin_write_DMA3_CONFIG(val) bfin_write32(DMA3_CFG, val)
+#define bfin_read_DMA3_X_COUNT() bfin_read32(DMA3_XCNT)
+#define bfin_write_DMA3_X_COUNT(val) bfin_write32(DMA3_XCNT, val)
+#define bfin_read_DMA3_X_MODIFY() bfin_read32(DMA3_XMOD)
+#define bfin_write_DMA3_X_MODIFY(val) bfin_write32(DMA3_XMOD, val)
+#define bfin_read_DMA3_Y_COUNT() bfin_read32(DMA3_YCNT)
+#define bfin_write_DMA3_Y_COUNT(val) bfin_write32(DMA3_YCNT, val)
+#define bfin_read_DMA3_Y_MODIFY() bfin_read32(DMA3_YMOD)
+#define bfin_write_DMA3_Y_MODIFY(val) bfin_write32(DMA3_YMOD, val)
+#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_DSCPTR_CUR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_DSCPTR_CUR, val)
+#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_ADDR_CUR)
+#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_ADDR_CUR, val)
+#define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_STAT)
+#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_STAT, val)
+#define bfin_read_DMA3_CURR_X_COUNT() bfin_read32(DMA3_XCNT_CUR)
+#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write32(DMA3_XCNT_CUR, val)
+#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read32(DMA3_YCNT_CUR)
+#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write32(DMA3_YCNT_CUR, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_DSCPTR_NXT)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_DSCPTR_NXT, val)
+#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_ADDRSTART)
+#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_ADDRSTART, val)
+#define bfin_read_DMA4_CONFIG() bfin_read32(DMA4_CFG)
+#define bfin_write_DMA4_CONFIG(val) bfin_write32(DMA4_CFG, val)
+#define bfin_read_DMA4_X_COUNT() bfin_read32(DMA4_XCNT)
+#define bfin_write_DMA4_X_COUNT(val) bfin_write32(DMA4_XCNT, val)
+#define bfin_read_DMA4_X_MODIFY() bfin_read32(DMA4_XMOD)
+#define bfin_write_DMA4_X_MODIFY(val) bfin_write32(DMA4_XMOD, val)
+#define bfin_read_DMA4_Y_COUNT() bfin_read32(DMA4_YCNT)
+#define bfin_write_DMA4_Y_COUNT(val) bfin_write32(DMA4_YCNT, val)
+#define bfin_read_DMA4_Y_MODIFY() bfin_read32(DMA4_YMOD)
+#define bfin_write_DMA4_Y_MODIFY(val) bfin_write32(DMA4_YMOD, val)
+#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_DSCPTR_CUR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_DSCPTR_CUR, val)
+#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_ADDR_CUR)
+#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_ADDR_CUR, val)
+#define bfin_read_DMA4_IRQ_STATUS() bfin_read32(DMA4_STAT)
+#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write32(DMA4_STAT, val)
+#define bfin_read_DMA4_CURR_X_COUNT() bfin_read32(DMA4_XCNT_CUR)
+#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write32(DMA4_XCNT_CUR, val)
+#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read32(DMA4_YCNT_CUR)
+#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write32(DMA4_YCNT_CUR, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_DSCPTR_NXT)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_DSCPTR_NXT, val)
+#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_ADDRSTART)
+#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_ADDRSTART, val)
+#define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CFG)
+#define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CFG, val)
+#define bfin_read_DMA5_X_COUNT() bfin_read32(DMA5_XCNT)
+#define bfin_write_DMA5_X_COUNT(val) bfin_write32(DMA5_XCNT, val)
+#define bfin_read_DMA5_X_MODIFY() bfin_read32(DMA5_XMOD)
+#define bfin_write_DMA5_X_MODIFY(val) bfin_write32(DMA5_XMOD, val)
+#define bfin_read_DMA5_Y_COUNT() bfin_read32(DMA5_YCNT)
+#define bfin_write_DMA5_Y_COUNT(val) bfin_write32(DMA5_YCNT, val)
+#define bfin_read_DMA5_Y_MODIFY() bfin_read32(DMA5_YMOD)
+#define bfin_write_DMA5_Y_MODIFY(val) bfin_write32(DMA5_YMOD, val)
+#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_DSCPTR_CUR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_DSCPTR_CUR, val)
+#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_ADDR_CUR)
+#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_ADDR_CUR, val)
+#define bfin_read_DMA5_IRQ_STATUS() bfin_read32(DMA5_STAT)
+#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write32(DMA5_STAT, val)
+#define bfin_read_DMA5_CURR_X_COUNT() bfin_read32(DMA5_XCNT_CUR)
+#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write32(DMA5_XCNT_CUR, val)
+#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read32(DMA5_YCNT_CUR)
+#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write32(DMA5_YCNT_CUR, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_DSCPTR_NXT)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_DSCPTR_NXT, val)
+#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_ADDRSTART)
+#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_ADDRSTART, val)
+#define bfin_read_DMA6_CONFIG() bfin_read32(DMA6_CFG)
+#define bfin_write_DMA6_CONFIG(val) bfin_write32(DMA6_CFG, val)
+#define bfin_read_DMA6_X_COUNT() bfin_read32(DMA6_XCNT)
+#define bfin_write_DMA6_X_COUNT(val) bfin_write32(DMA6_XCNT, val)
+#define bfin_read_DMA6_X_MODIFY() bfin_read32(DMA6_XMOD)
+#define bfin_write_DMA6_X_MODIFY(val) bfin_write32(DMA6_XMOD, val)
+#define bfin_read_DMA6_Y_COUNT() bfin_read32(DMA6_YCNT)
+#define bfin_write_DMA6_Y_COUNT(val) bfin_write32(DMA6_YCNT, val)
+#define bfin_read_DMA6_Y_MODIFY() bfin_read32(DMA6_YMOD)
+#define bfin_write_DMA6_Y_MODIFY(val) bfin_write32(DMA6_YMOD, val)
+#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_DSCPTR_CUR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_DSCPTR_CUR, val)
+#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_ADDR_CUR)
+#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_ADDR_CUR, val)
+#define bfin_read_DMA6_IRQ_STATUS() bfin_read32(DMA6_STAT)
+#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write32(DMA6_STAT, val)
+#define bfin_read_DMA6_CURR_X_COUNT() bfin_read32(DMA6_XCNT_CUR)
+#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write32(DMA6_XCNT_CUR, val)
+#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read32(DMA6_YCNT_CUR)
+#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write32(DMA6_YCNT_CUR, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_DSCPTR_NXT)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_DSCPTR_NXT, val)
+#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_ADDRSTART)
+#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_ADDRSTART, val)
+#define bfin_read_DMA7_CONFIG() bfin_read32(DMA7_CFG)
+#define bfin_write_DMA7_CONFIG(val) bfin_write32(DMA7_CFG, val)
+#define bfin_read_DMA7_X_COUNT() bfin_read32(DMA7_XCNT)
+#define bfin_write_DMA7_X_COUNT(val) bfin_write32(DMA7_XCNT, val)
+#define bfin_read_DMA7_X_MODIFY() bfin_read32(DMA7_XMOD)
+#define bfin_write_DMA7_X_MODIFY(val) bfin_write32(DMA7_XMOD, val)
+#define bfin_read_DMA7_Y_COUNT() bfin_read32(DMA7_YCNT)
+#define bfin_write_DMA7_Y_COUNT(val) bfin_write32(DMA7_YCNT, val)
+#define bfin_read_DMA7_Y_MODIFY() bfin_read32(DMA7_YMOD)
+#define bfin_write_DMA7_Y_MODIFY(val) bfin_write32(DMA7_YMOD, val)
+#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_DSCPTR_CUR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_DSCPTR_CUR, val)
+#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_ADDR_CUR)
+#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_ADDR_CUR, val)
+#define bfin_read_DMA7_IRQ_STATUS() bfin_read32(DMA7_STAT)
+#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write32(DMA7_STAT, val)
+#define bfin_read_DMA7_CURR_X_COUNT() bfin_read32(DMA7_XCNT_CUR)
+#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write32(DMA7_XCNT_CUR, val)
+#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read32(DMA7_YCNT_CUR)
+#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write32(DMA7_YCNT_CUR, val)
+#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_DSCPTR_NXT)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_DSCPTR_NXT, val)
+#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_ADDRSTART)
+#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_ADDRSTART, val)
+#define bfin_read_DMA8_CONFIG() bfin_read32(DMA8_CFG)
+#define bfin_write_DMA8_CONFIG(val) bfin_write32(DMA8_CFG, val)
+#define bfin_read_DMA8_X_COUNT() bfin_read32(DMA8_XCNT)
+#define bfin_write_DMA8_X_COUNT(val) bfin_write32(DMA8_XCNT, val)
+#define bfin_read_DMA8_X_MODIFY() bfin_read32(DMA8_XMOD)
+#define bfin_write_DMA8_X_MODIFY(val) bfin_write32(DMA8_XMOD, val)
+#define bfin_read_DMA8_Y_COUNT() bfin_read32(DMA8_YCNT)
+#define bfin_write_DMA8_Y_COUNT(val) bfin_write32(DMA8_YCNT, val)
+#define bfin_read_DMA8_Y_MODIFY() bfin_read32(DMA8_YMOD)
+#define bfin_write_DMA8_Y_MODIFY(val) bfin_write32(DMA8_YMOD, val)
+#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_DSCPTR_CUR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_DSCPTR_CUR, val)
+#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_ADDR_CUR)
+#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_ADDR_CUR, val)
+#define bfin_read_DMA8_IRQ_STATUS() bfin_read32(DMA8_STAT)
+#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write32(DMA8_STAT, val)
+#define bfin_read_DMA8_CURR_X_COUNT() bfin_read32(DMA8_XCNT_CUR)
+#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write32(DMA8_XCNT_CUR, val)
+#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read32(DMA8_YCNT_CUR)
+#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write32(DMA8_YCNT_CUR, val)
+#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_DSCPTR_NXT)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_DSCPTR_NXT, val)
+#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_ADDRSTART)
+#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_ADDRSTART, val)
+#define bfin_read_DMA9_CONFIG() bfin_read32(DMA9_CFG)
+#define bfin_write_DMA9_CONFIG(val) bfin_write32(DMA9_CFG, val)
+#define bfin_read_DMA9_X_COUNT() bfin_read32(DMA9_XCNT)
+#define bfin_write_DMA9_X_COUNT(val) bfin_write32(DMA9_XCNT, val)
+#define bfin_read_DMA9_X_MODIFY() bfin_read32(DMA9_XMOD)
+#define bfin_write_DMA9_X_MODIFY(val) bfin_write32(DMA9_XMOD, val)
+#define bfin_read_DMA9_Y_COUNT() bfin_read32(DMA9_YCNT)
+#define bfin_write_DMA9_Y_COUNT(val) bfin_write32(DMA9_YCNT, val)
+#define bfin_read_DMA9_Y_MODIFY() bfin_read32(DMA9_YMOD)
+#define bfin_write_DMA9_Y_MODIFY(val) bfin_write32(DMA9_YMOD, val)
+#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_DSCPTR_CUR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_DSCPTR_CUR, val)
+#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_ADDR_CUR)
+#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_ADDR_CUR, val)
+#define bfin_read_DMA9_IRQ_STATUS() bfin_read32(DMA9_STAT)
+#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write32(DMA9_STAT, val)
+#define bfin_read_DMA9_CURR_X_COUNT() bfin_read32(DMA9_XCNT_CUR)
+#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write32(DMA9_XCNT_CUR, val)
+#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read32(DMA9_YCNT_CUR)
+#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write32(DMA9_YCNT_CUR, val)
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_NXT)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_NXT, val)
+#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_ADDRSTART)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_ADDRSTART, val)
+#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CFG)
+#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CFG, val)
+#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_XCNT)
+#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_XCNT, val)
+#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_XMOD)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_XMOD, val)
+#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_YCNT)
+#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_YCNT, val)
+#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_YMOD)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_YMOD, val)
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_CUR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_CUR, val)
+#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_ADDR_CUR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_ADDR_CUR, val)
+#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_STAT)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_STAT, val)
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_XCNT_CUR)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_XCNT_CUR, val)
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_YCNT_CUR)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_YCNT_CUR, val)
+#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_DSCPTR_NXT)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_DSCPTR_NXT, val)
+#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_ADDRSTART)
+#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_ADDRSTART, val)
+#define bfin_read_DMA11_CONFIG() bfin_read32(DMA11_CFG)
+#define bfin_write_DMA11_CONFIG(val) bfin_write32(DMA11_CFG, val)
+#define bfin_read_DMA11_X_COUNT() bfin_read32(DMA11_XCNT)
+#define bfin_write_DMA11_X_COUNT(val) bfin_write32(DMA11_XCNT, val)
+#define bfin_read_DMA11_X_MODIFY() bfin_read32(DMA11_XMOD)
+#define bfin_write_DMA11_X_MODIFY(val) bfin_write32(DMA11_XMOD, val)
+#define bfin_read_DMA11_Y_COUNT() bfin_read32(DMA11_YCNT)
+#define bfin_write_DMA11_Y_COUNT(val) bfin_write32(DMA11_YCNT, val)
+#define bfin_read_DMA11_Y_MODIFY() bfin_read32(DMA11_YMOD)
+#define bfin_write_DMA11_Y_MODIFY(val) bfin_write32(DMA11_YMOD, val)
+#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_DSCPTR_CUR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_DSCPTR_CUR, val)
+#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_ADDR_CUR)
+#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_ADDR_CUR, val)
+#define bfin_read_DMA11_IRQ_STATUS() bfin_read32(DMA11_STAT)
+#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write32(DMA11_STAT, val)
+#define bfin_read_DMA11_CURR_X_COUNT() bfin_read32(DMA11_XCNT_CUR)
+#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write32(DMA11_XCNT_CUR, val)
+#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read32(DMA11_YCNT_CUR)
+#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write32(DMA11_YCNT_CUR, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_DSCPTR_NXT)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_DSCPTR_NXT, val)
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_ADDRSTART)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_ADDRSTART, val)
+#define bfin_read_MDMA_S0_CONFIG() bfin_read32(MDMA_S0_CFG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write32(MDMA_S0_CFG, val)
+#define bfin_read_MDMA_S0_X_COUNT() bfin_read32(MDMA_S0_XCNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write32(MDMA_S0_XCNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY() bfin_read32(MDMA_S0_XMOD)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write32(MDMA_S0_XMOD, val)
+#define bfin_read_MDMA_S0_Y_COUNT() bfin_read32(MDMA_S0_YCNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write32(MDMA_S0_YCNT, val)
+#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read32(MDMA_S0_YMOD)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write32(MDMA_S0_YMOD, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_DSCPTR_CUR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_DSCPTR_CUR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_ADDR_CUR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_ADDR_CUR, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read32(MDMA_S0_STAT)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write32(MDMA_S0_STAT, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read32(MDMA_S0_XCNT_CUR)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write32(MDMA_S0_XCNT_CUR, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read32(MDMA_S0_YCNT_CUR)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write32(MDMA_S0_YCNT_CUR, val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_DSCPTR_NXT)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_DSCPTR_NXT, val)
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_ADDRSTART)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_ADDRSTART, val)
+#define bfin_read_MDMA_D0_CONFIG() bfin_read32(MDMA_D0_CFG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write32(MDMA_D0_CFG, val)
+#define bfin_read_MDMA_D0_X_COUNT() bfin_read32(MDMA_D0_XCNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write32(MDMA_D0_XCNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY() bfin_read32(MDMA_D0_XMOD)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write32(MDMA_D0_XMOD, val)
+#define bfin_read_MDMA_D0_Y_COUNT() bfin_read32(MDMA_D0_YCNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write32(MDMA_D0_YCNT, val)
+#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read32(MDMA_D0_YMOD)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write32(MDMA_D0_YMOD, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_DSCPTR_CUR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_DSCPTR_CUR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_ADDR_CUR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_ADDR_CUR, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read32(MDMA_D0_STAT)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write32(MDMA_D0_STAT, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read32(MDMA_D0_XCNT_CUR)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write32(MDMA_D0_XCNT_CUR, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read32(MDMA_D0_YCNT_CUR)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write32(MDMA_D0_YCNT_CUR, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_DSCPTR_NXT)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_DSCPTR_NXT, val)
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_ADDRSTART)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_ADDRSTART, val)
+#define bfin_read_MDMA_S1_CONFIG() bfin_read32(MDMA_S1_CFG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write32(MDMA_S1_CFG, val)
+#define bfin_read_MDMA_S1_X_COUNT() bfin_read32(MDMA_S1_XCNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write32(MDMA_S1_XCNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY() bfin_read32(MDMA_S1_XMOD)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write32(MDMA_S1_XMOD, val)
+#define bfin_read_MDMA_S1_Y_COUNT() bfin_read32(MDMA_S1_YCNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write32(MDMA_S1_YCNT, val)
+#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read32(MDMA_S1_YMOD)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write32(MDMA_S1_YMOD, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_DSCPTR_CUR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_DSCPTR_CUR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_ADDR_CUR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_ADDR_CUR, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read32(MDMA_S1_STAT)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write32(MDMA_S1_STAT, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read32(MDMA_S1_XCNT_CUR)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write32(MDMA_S1_XCNT_CUR, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read32(MDMA_S1_YCNT_CUR)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write32(MDMA_S1_YCNT_CUR, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_DSCPTR_NXT)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_DSCPTR_NXT, val)
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_ADDRSTART)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_ADDRSTART, val)
+#define bfin_read_MDMA_D1_CONFIG() bfin_read32(MDMA_D1_CFG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write32(MDMA_D1_CFG, val)
+#define bfin_read_MDMA_D1_X_COUNT() bfin_read32(MDMA_D1_XCNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write32(MDMA_D1_XCNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY() bfin_read32(MDMA_D1_XMOD)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write32(MDMA_D1_XMOD, val)
+#define bfin_read_MDMA_D1_Y_COUNT() bfin_read32(MDMA_D1_YCNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write32(MDMA_D1_YCNT, val)
+#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read32(MDMA_D1_YMOD)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write32(MDMA_D1_YMOD, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_DSCPTR_CUR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_DSCPTR_CUR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_ADDR_CUR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_ADDR_CUR, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read32(MDMA_D1_STAT)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write32(MDMA_D1_STAT, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read32(MDMA_D1_XCNT_CUR)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write32(MDMA_D1_XCNT_CUR, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read32(MDMA_D1_YCNT_CUR)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write32(MDMA_D1_YCNT_CUR, val)
+
+#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_CTL() bfin_read32(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val) bfin_write32(WDOG_CTL, val)
+#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
+#define bfin_read_SPI_BAUD() bfin_read32(SPI0_CLK)
+#define bfin_write_SPI_BAUD(val) bfin_write32(SPI0_CLK, val)
+
+#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
+#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
+#define bfin_write_PORTD_FER_CLR(val) bfin_write32(PORTD_FER_CLR, val)
+#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
+#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
+#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
+#define bfin_write_PORTG_FER_CLR(val) bfin_write32(PORTG_FER_CLR, val)
+#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
+
+#define bfin_read_RSI_CLK_CONTROL()    bfin_read16(RSI_CLK_CONTROL)
+#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
+#define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)
+#define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)
+#define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)
+#define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)
+#define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)
+#define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)
+#define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)
+#define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)
+#define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)
+#define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)
+#define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)
+#define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)
+#define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)
+#define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)
+#define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)
+#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
+#define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)
+#define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)
+#define bfin_read_RSI_DATA_CONTROL()   bfin_read16(RSI_DATA_CONTROL)
+#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
+#define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)
+#define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)
+#define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)
+#define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)
+#define bfin_read_RSI_STATUSCL()       bfin_read16(RSI_STATUSCL)
+#define bfin_write_RSI_STATUSCL(val)   bfin_write16(RSI_STATUSCL, val)
+#define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)
+#define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)
+#define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)
+#define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)
+#define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)
+#define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)
+#define bfin_read_RSI_CEATA_CONTROL()  bfin_read16(RSI_CEATA_CONTROL)
+#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
+#define bfin_read_RSI_BLKSZ()          bfin_read16(RSI_BLKSZ)
+#define bfin_write_RSI_BLKSZ(val)      bfin_write16(RSI_BLKSZ, val)
+#define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)
+#define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)
+#define bfin_read_RSI_ESTAT()          bfin_read32(RSI_ESTAT)
+#define bfin_write_RSI_ESTAT(val)      bfin_write32(RSI_ESTAT, val)
+#define bfin_read_RSI_EMASK()          bfin_read32(RSI_EMASK)
+#define bfin_write_RSI_EMASK(val)      bfin_write32(RSI_EMASK, val)
+#define bfin_read_RSI_CONFIG()         bfin_read16(RSI_CONFIG)
+#define bfin_write_RSI_CONFIG(val)     bfin_write16(RSI_CONFIG, val)
+#define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)
+#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
+#define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)
+#define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)
+#define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)
+#define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)
+#define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)
+#define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)
+#define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)
+#define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF609_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf609/BF609_def.h b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
new file mode 100644
index 0000000..39b740f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/BF609_def.h
@@ -0,0 +1,3758 @@ 
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF609_proc__
+#define __BFIN_DEF_ADSP_BF609_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#define CNT_CFG                     0xFFC00400         /* CNT0 Configuration Register */
+#define CNT_IMSK                    0xFFC00404         /* CNT0 Interrupt Mask Register */
+#define CNT_STAT                    0xFFC00408         /* CNT0 Status Register */
+#define CNT_CMD                     0xFFC0040C         /* CNT0 Command Register */
+#define CNT_DEBNCE                  0xFFC00410         /* CNT0 Debounce Register */
+#define CNT_CNTR                    0xFFC00414         /* CNT0 Counter Register */
+#define CNT_MAX                     0xFFC00418         /* CNT0 Maximum Count Register */
+#define CNT_MIN                     0xFFC0041C         /* CNT0 Minimum Count Register */
+
+#define RSI_CLK_CONTROL             0xFFC00604         /* RSI0 Clock Control Register */
+#define RSI_ARGUMENT                0xFFC00608         /* RSI0 Argument Register */
+#define RSI_COMMAND                 0xFFC0060C         /* RSI0 Command Register */
+#define RSI_RESP_CMD                0xFFC00610         /* RSI0 Response Command Register */
+#define RSI_RESPONSE0               0xFFC00614         /* RSI0 Response 0 Register */
+#define RSI_RESPONSE1               0xFFC00618         /* RSI0 Response 1 Register */
+#define RSI_RESPONSE2               0xFFC0061C         /* RSI0 Response 2 Register */
+#define RSI_RESPONSE3               0xFFC00620         /* RSI0 Response 3 Register */
+#define RSI_DATA_TIMER              0xFFC00624         /* RSI0 Data Timer Register */
+#define RSI_DATA_LGTH               0xFFC00628         /* RSI0 Data Length Register */
+#define RSI_DATA_CONTROL            0xFFC0062C         /* RSI0 Data Control Register */
+#define RSI_DATA_CNT                0xFFC00630         /* RSI0 Data Count Register */
+#define RSI_STATUS                  0xFFC00634         /* RSI0 Status Register */
+#define RSI_STATUSCL                0xFFC00638         /* RSI0 Status Clear Register */
+#define RSI_IMSK0                   0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
+#define RSI_IMSK1                   0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
+#define RSI_FIFO_CNT                0xFFC00648         /* RSI0 FIFO Counter Register */
+#define RSI_CEATA_CONTROL           0xFFC0064C         /* RSI0 This register contains bit to dis CCS gen */
+#define RSI_BOOT_TCNTR              0xFFC00650         /* RSI0 Boot Timing Counter Register */
+#define RSI_BACK_TOUT               0xFFC00654         /* RSI0 Boot Acknowledge Timeout Register */
+#define RSI_SLP_WKUP_TOUT           0xFFC00658         /* RSI0 Sleep Wakeup Timeout Register */
+#define RSI_BLKSZ                   0xFFC0065C         /* RSI0 Block Size Register */
+#define RSI_FIFO                    0xFFC00680         /* RSI0 Data FIFO Register */
+#define RSI_ESTAT                   0xFFC006C0         /* RSI0 Exception Status Register */
+#define RSI_EMASK                   0xFFC006C4         /* RSI0 Exception Mask Register */
+#define RSI_CONFIG                  0xFFC006C8         /* RSI0 Configuration Register */
+#define RSI_RD_WAIT_EN              0xFFC006CC         /* RSI0 Read Wait Enable Register */
+#define RSI_PID0                    0xFFC006D0         /* RSI0 Peripheral Identification Register */
+#define RSI_PID1                    0xFFC006D4         /* RSI0 Peripheral Identification Register */
+#define RSI_PID2                    0xFFC006D8         /* RSI0 Peripheral Identification Register */
+#define RSI_PID3                    0xFFC006DC         /* RSI0 Peripheral Identification Register */
+
+#define CAN0_MC1                    0xFFC00A00         /* CAN0 Mailbox Configuration Register 1 */
+#define CAN0_MD1                    0xFFC00A04         /* CAN0 Mailbox Direction Register 1 */
+#define CAN0_TRS1                   0xFFC00A08         /* CAN0 Transmission Request Set Register 1 */
+#define CAN0_TRR1                   0xFFC00A0C         /* CAN0 Transmission Request Reset Register 1 */
+#define CAN0_TA1                    0xFFC00A10         /* CAN0 Transmission Acknowledge Register 1 */
+#define CAN0_AA1                    0xFFC00A14         /* CAN0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1                   0xFFC00A18         /* CAN0 Receive Message Pending Register 1 */
+#define CAN0_RML1                   0xFFC00A1C         /* CAN0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1                 0xFFC00A20         /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1                 0xFFC00A24         /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1                  0xFFC00A28         /* CAN0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1                   0xFFC00A2C         /* CAN0 Remote Frame Handling Register 1 */
+#define CAN0_OPSS1                  0xFFC00A30         /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
+#define CAN0_MC2                    0xFFC00A40         /* CAN0 Mailbox Configuration Register 2 */
+#define CAN0_MD2                    0xFFC00A44         /* CAN0 Mailbox Direction Register 2 */
+#define CAN0_TRS2                   0xFFC00A48         /* CAN0 Transmission Request Set Register 2 */
+#define CAN0_TRR2                   0xFFC00A4C         /* CAN0 Transmission Request Reset Register 2 */
+#define CAN0_TA2                    0xFFC00A50         /* CAN0 Transmission Acknowledge Register 2 */
+#define CAN0_AA2                    0xFFC00A54         /* CAN0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2                   0xFFC00A58         /* CAN0 Receive Message Pending Register 2 */
+#define CAN0_RML2                   0xFFC00A5C         /* CAN0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2                 0xFFC00A60         /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2                 0xFFC00A64         /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2                  0xFFC00A68         /* CAN0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2                   0xFFC00A6C         /* CAN0 Remote Frame Handling Register 2 */
+#define CAN0_OPSS2                  0xFFC00A70         /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
+#define CAN0_CLK                    0xFFC00A80         /* CAN0 Clock Register */
+#define CAN0_TIMING                 0xFFC00A84         /* CAN0 Timing Register */
+#define CAN0_DBG                    0xFFC00A88         /* CAN0 Debug Register */
+#define CAN0_STAT                   0xFFC00A8C         /* CAN0 Status Register */
+#define CAN0_CEC                    0xFFC00A90         /* CAN0 Error Counter Register */
+#define CAN0_GIS                    0xFFC00A94         /* CAN0 Global CAN Interrupt Status */
+#define CAN0_GIM                    0xFFC00A98         /* CAN0 Global CAN Interrupt Mask */
+#define CAN0_GIF                    0xFFC00A9C         /* CAN0 Global CAN Interrupt Flag */
+#define CAN0_CTL                    0xFFC00AA0         /* CAN0 CAN Master Control Register */
+#define CAN0_INT                    0xFFC00AA4         /* CAN0 Interrupt Pending Register */
+#define CAN0_MBTD                   0xFFC00AAC         /* CAN0 Temporary Mailbox Disable Register */
+#define CAN0_EWR                    0xFFC00AB0         /* CAN0 Error Counter Warning Level Register */
+#define CAN0_ESR                    0xFFC00AB4         /* CAN0 Error Status Register */
+#define CAN0_UCCNT                  0xFFC00AC4         /* CAN0 Universal Counter Register */
+#define CAN0_UCRC                   0xFFC00AC8         /* CAN0 Universal Counter Reload/Capture Register */
+#define CAN0_UCCNF                  0xFFC00ACC         /* CAN0 Universal Counter Configuration Mode Register */
+#define CAN0_AM00L                  0xFFC00B00         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM01L                  0xFFC00B08         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM02L                  0xFFC00B10         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM03L                  0xFFC00B18         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM04L                  0xFFC00B20         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM05L                  0xFFC00B28         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM06L                  0xFFC00B30         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM07L                  0xFFC00B38         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM08L                  0xFFC00B40         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM09L                  0xFFC00B48         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM10L                  0xFFC00B50         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM11L                  0xFFC00B58         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM12L                  0xFFC00B60         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM13L                  0xFFC00B68         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM14L                  0xFFC00B70         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM15L                  0xFFC00B78         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM16L                  0xFFC00B80         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM17L                  0xFFC00B88         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM18L                  0xFFC00B90         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM19L                  0xFFC00B98         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM20L                  0xFFC00BA0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM21L                  0xFFC00BA8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM22L                  0xFFC00BB0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM23L                  0xFFC00BB8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM24L                  0xFFC00BC0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM25L                  0xFFC00BC8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM26L                  0xFFC00BD0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM27L                  0xFFC00BD8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM28L                  0xFFC00BE0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM29L                  0xFFC00BE8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM30L                  0xFFC00BF0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM31L                  0xFFC00BF8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM00H                  0xFFC00B04         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM01H                  0xFFC00B0C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM02H                  0xFFC00B14         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM03H                  0xFFC00B1C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM04H                  0xFFC00B24         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM05H                  0xFFC00B2C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM06H                  0xFFC00B34         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM07H                  0xFFC00B3C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM08H                  0xFFC00B44         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM09H                  0xFFC00B4C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM10H                  0xFFC00B54         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM11H                  0xFFC00B5C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM12H                  0xFFC00B64         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM13H                  0xFFC00B6C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM14H                  0xFFC00B74         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM15H                  0xFFC00B7C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM16H                  0xFFC00B84         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM17H                  0xFFC00B8C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM18H                  0xFFC00B94         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM19H                  0xFFC00B9C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM20H                  0xFFC00BA4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM21H                  0xFFC00BAC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM22H                  0xFFC00BB4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM23H                  0xFFC00BBC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM24H                  0xFFC00BC4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM25H                  0xFFC00BCC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM26H                  0xFFC00BD4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM27H                  0xFFC00BDC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM28H                  0xFFC00BE4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM29H                  0xFFC00BEC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM30H                  0xFFC00BF4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM31H                  0xFFC00BFC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_MB00_DATA0             0xFFC00C00         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB01_DATA0             0xFFC00C20         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB02_DATA0             0xFFC00C40         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB03_DATA0             0xFFC00C60         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB04_DATA0             0xFFC00C80         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB05_DATA0             0xFFC00CA0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB06_DATA0             0xFFC00CC0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB07_DATA0             0xFFC00CE0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB08_DATA0             0xFFC00D00         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB09_DATA0             0xFFC00D20         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB10_DATA0             0xFFC00D40         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB11_DATA0             0xFFC00D60         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB12_DATA0             0xFFC00D80         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB13_DATA0             0xFFC00DA0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB14_DATA0             0xFFC00DC0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB15_DATA0             0xFFC00DE0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB16_DATA0             0xFFC00E00         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB17_DATA0             0xFFC00E20         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB18_DATA0             0xFFC00E40         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB19_DATA0             0xFFC00E60         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB20_DATA0             0xFFC00E80         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB21_DATA0             0xFFC00EA0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB22_DATA0             0xFFC00EC0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB23_DATA0             0xFFC00EE0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB24_DATA0             0xFFC00F00         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB25_DATA0             0xFFC00F20         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB26_DATA0             0xFFC00F40         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB27_DATA0             0xFFC00F60         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB28_DATA0             0xFFC00F80         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB29_DATA0             0xFFC00FA0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB30_DATA0             0xFFC00FC0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB31_DATA0             0xFFC00FE0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB00_DATA1             0xFFC00C04         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB01_DATA1             0xFFC00C24         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB02_DATA1             0xFFC00C44         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB03_DATA1             0xFFC00C64         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB04_DATA1             0xFFC00C84         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB05_DATA1             0xFFC00CA4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB06_DATA1             0xFFC00CC4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB07_DATA1             0xFFC00CE4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB08_DATA1             0xFFC00D04         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB09_DATA1             0xFFC00D24         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB10_DATA1             0xFFC00D44         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB11_DATA1             0xFFC00D64         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB12_DATA1             0xFFC00D84         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB13_DATA1             0xFFC00DA4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB14_DATA1             0xFFC00DC4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB15_DATA1             0xFFC00DE4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB16_DATA1             0xFFC00E04         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB17_DATA1             0xFFC00E24         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB18_DATA1             0xFFC00E44         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB19_DATA1             0xFFC00E64         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB20_DATA1             0xFFC00E84         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB21_DATA1             0xFFC00EA4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB22_DATA1             0xFFC00EC4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB23_DATA1             0xFFC00EE4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB24_DATA1             0xFFC00F04         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB25_DATA1             0xFFC00F24         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB26_DATA1             0xFFC00F44         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB27_DATA1             0xFFC00F64         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB28_DATA1             0xFFC00F84         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB29_DATA1             0xFFC00FA4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB30_DATA1             0xFFC00FC4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB31_DATA1             0xFFC00FE4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB00_DATA2             0xFFC00C08         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB01_DATA2             0xFFC00C28         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB02_DATA2             0xFFC00C48         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB03_DATA2             0xFFC00C68         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB04_DATA2             0xFFC00C88         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB05_DATA2             0xFFC00CA8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB06_DATA2             0xFFC00CC8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB07_DATA2             0xFFC00CE8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB08_DATA2             0xFFC00D08         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB09_DATA2             0xFFC00D28         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB10_DATA2             0xFFC00D48         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB11_DATA2             0xFFC00D68         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB12_DATA2             0xFFC00D88         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB13_DATA2             0xFFC00DA8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB14_DATA2             0xFFC00DC8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB15_DATA2             0xFFC00DE8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB16_DATA2             0xFFC00E08         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB17_DATA2             0xFFC00E28         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB18_DATA2             0xFFC00E48         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB19_DATA2             0xFFC00E68         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB20_DATA2             0xFFC00E88         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB21_DATA2             0xFFC00EA8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB22_DATA2             0xFFC00EC8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB23_DATA2             0xFFC00EE8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB24_DATA2             0xFFC00F08         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB25_DATA2             0xFFC00F28         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB26_DATA2             0xFFC00F48         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB27_DATA2             0xFFC00F68         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB28_DATA2             0xFFC00F88         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB29_DATA2             0xFFC00FA8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB30_DATA2             0xFFC00FC8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB31_DATA2             0xFFC00FE8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB00_DATA3             0xFFC00C0C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB01_DATA3             0xFFC00C2C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB02_DATA3             0xFFC00C4C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB03_DATA3             0xFFC00C6C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB04_DATA3             0xFFC00C8C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB05_DATA3             0xFFC00CAC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB06_DATA3             0xFFC00CCC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB07_DATA3             0xFFC00CEC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB08_DATA3             0xFFC00D0C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB09_DATA3             0xFFC00D2C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB10_DATA3             0xFFC00D4C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB11_DATA3             0xFFC00D6C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB12_DATA3             0xFFC00D8C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB13_DATA3             0xFFC00DAC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB14_DATA3             0xFFC00DCC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB15_DATA3             0xFFC00DEC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB16_DATA3             0xFFC00E0C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB17_DATA3             0xFFC00E2C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB18_DATA3             0xFFC00E4C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB19_DATA3             0xFFC00E6C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB20_DATA3             0xFFC00E8C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB21_DATA3             0xFFC00EAC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB22_DATA3             0xFFC00ECC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB23_DATA3             0xFFC00EEC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB24_DATA3             0xFFC00F0C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB25_DATA3             0xFFC00F2C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB26_DATA3             0xFFC00F4C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB27_DATA3             0xFFC00F6C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB28_DATA3             0xFFC00F8C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB29_DATA3             0xFFC00FAC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB30_DATA3             0xFFC00FCC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB31_DATA3             0xFFC00FEC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB00_LENGTH            0xFFC00C10         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB01_LENGTH            0xFFC00C30         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB02_LENGTH            0xFFC00C50         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB03_LENGTH            0xFFC00C70         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB04_LENGTH            0xFFC00C90         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB05_LENGTH            0xFFC00CB0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB06_LENGTH            0xFFC00CD0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB07_LENGTH            0xFFC00CF0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB08_LENGTH            0xFFC00D10         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB09_LENGTH            0xFFC00D30         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB10_LENGTH            0xFFC00D50         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB11_LENGTH            0xFFC00D70         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB12_LENGTH            0xFFC00D90         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB13_LENGTH            0xFFC00DB0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB14_LENGTH            0xFFC00DD0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB15_LENGTH            0xFFC00DF0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB16_LENGTH            0xFFC00E10         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB17_LENGTH            0xFFC00E30         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB18_LENGTH            0xFFC00E50         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB19_LENGTH            0xFFC00E70         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB20_LENGTH            0xFFC00E90         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB21_LENGTH            0xFFC00EB0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB22_LENGTH            0xFFC00ED0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB23_LENGTH            0xFFC00EF0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB24_LENGTH            0xFFC00F10         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB25_LENGTH            0xFFC00F30         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB26_LENGTH            0xFFC00F50         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB27_LENGTH            0xFFC00F70         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB28_LENGTH            0xFFC00F90         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB29_LENGTH            0xFFC00FB0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB30_LENGTH            0xFFC00FD0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB31_LENGTH            0xFFC00FF0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB00_TIMESTAMP         0xFFC00C14         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB01_TIMESTAMP         0xFFC00C34         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB02_TIMESTAMP         0xFFC00C54         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB03_TIMESTAMP         0xFFC00C74         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB04_TIMESTAMP         0xFFC00C94         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB05_TIMESTAMP         0xFFC00CB4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB06_TIMESTAMP         0xFFC00CD4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB07_TIMESTAMP         0xFFC00CF4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB08_TIMESTAMP         0xFFC00D14         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB09_TIMESTAMP         0xFFC00D34         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB10_TIMESTAMP         0xFFC00D54         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB11_TIMESTAMP         0xFFC00D74         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB12_TIMESTAMP         0xFFC00D94         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB13_TIMESTAMP         0xFFC00DB4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB14_TIMESTAMP         0xFFC00DD4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB15_TIMESTAMP         0xFFC00DF4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB16_TIMESTAMP         0xFFC00E14         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB17_TIMESTAMP         0xFFC00E34         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB18_TIMESTAMP         0xFFC00E54         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB19_TIMESTAMP         0xFFC00E74         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB20_TIMESTAMP         0xFFC00E94         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB21_TIMESTAMP         0xFFC00EB4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB22_TIMESTAMP         0xFFC00ED4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB23_TIMESTAMP         0xFFC00EF4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB24_TIMESTAMP         0xFFC00F14         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB25_TIMESTAMP         0xFFC00F34         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB26_TIMESTAMP         0xFFC00F54         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB27_TIMESTAMP         0xFFC00F74         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB28_TIMESTAMP         0xFFC00F94         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB29_TIMESTAMP         0xFFC00FB4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB30_TIMESTAMP         0xFFC00FD4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB31_TIMESTAMP         0xFFC00FF4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB00_ID0               0xFFC00C18         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB01_ID0               0xFFC00C38         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB02_ID0               0xFFC00C58         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB03_ID0               0xFFC00C78         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB04_ID0               0xFFC00C98         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB05_ID0               0xFFC00CB8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB06_ID0               0xFFC00CD8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB07_ID0               0xFFC00CF8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB08_ID0               0xFFC00D18         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB09_ID0               0xFFC00D38         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB10_ID0               0xFFC00D58         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB11_ID0               0xFFC00D78         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB12_ID0               0xFFC00D98         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB13_ID0               0xFFC00DB8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB14_ID0               0xFFC00DD8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB15_ID0               0xFFC00DF8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB16_ID0               0xFFC00E18         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB17_ID0               0xFFC00E38         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB18_ID0               0xFFC00E58         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB19_ID0               0xFFC00E78         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB20_ID0               0xFFC00E98         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB21_ID0               0xFFC00EB8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB22_ID0               0xFFC00ED8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB23_ID0               0xFFC00EF8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB24_ID0               0xFFC00F18         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB25_ID0               0xFFC00F38         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB26_ID0               0xFFC00F58         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB27_ID0               0xFFC00F78         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB28_ID0               0xFFC00F98         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB29_ID0               0xFFC00FB8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB30_ID0               0xFFC00FD8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB31_ID0               0xFFC00FF8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB00_ID1               0xFFC00C1C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB01_ID1               0xFFC00C3C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB02_ID1               0xFFC00C5C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB03_ID1               0xFFC00C7C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB04_ID1               0xFFC00C9C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB05_ID1               0xFFC00CBC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB06_ID1               0xFFC00CDC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB07_ID1               0xFFC00CFC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB08_ID1               0xFFC00D1C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB09_ID1               0xFFC00D3C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB10_ID1               0xFFC00D5C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB11_ID1               0xFFC00D7C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB12_ID1               0xFFC00D9C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB13_ID1               0xFFC00DBC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB14_ID1               0xFFC00DDC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB15_ID1               0xFFC00DFC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB16_ID1               0xFFC00E1C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB17_ID1               0xFFC00E3C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB18_ID1               0xFFC00E5C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB19_ID1               0xFFC00E7C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB20_ID1               0xFFC00E9C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB21_ID1               0xFFC00EBC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB22_ID1               0xFFC00EDC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB23_ID1               0xFFC00EFC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB24_ID1               0xFFC00F1C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB25_ID1               0xFFC00F3C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB26_ID1               0xFFC00F5C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB27_ID1               0xFFC00F7C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB28_ID1               0xFFC00F9C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB29_ID1               0xFFC00FBC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB30_ID1               0xFFC00FDC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB31_ID1               0xFFC00FFC         /* CAN0 Mailbox Word 7 Register */
+#define LP0_CTL                     0xFFC01000         /* LP0 Control Register */
+#define LP0_STAT                    0xFFC01004         /* LP0 Status Register */
+#define LP0_DIV                     0xFFC01008         /* LP0 Clock Divider Value */
+#define LP0_CNT                     0xFFC0100C         /* LP0 Current Count Value of Clock Divider */
+#define LP0_TX                      0xFFC01010         /* LP0 Transmit Buffer */
+#define LP0_RX                      0xFFC01014         /* LP0 Receive Buffer */
+#define LP0_TXIN_SHDW               0xFFC01018         /* LP0 Shadow Input Transmit Buffer */
+#define LP0_TXOUT_SHDW              0xFFC0101C         /* LP0 Shadow Output Transmit Buffer */
+#define LP1_CTL                     0xFFC01100         /* LP1 Control Register */
+#define LP1_STAT                    0xFFC01104         /* LP1 Status Register */
+#define LP1_DIV                     0xFFC01108         /* LP1 Clock Divider Value */
+#define LP1_CNT                     0xFFC0110C         /* LP1 Current Count Value of Clock Divider */
+#define LP1_TX                      0xFFC01110         /* LP1 Transmit Buffer */
+#define LP1_RX                      0xFFC01114         /* LP1 Receive Buffer */
+#define LP1_TXIN_SHDW               0xFFC01118         /* LP1 Shadow Input Transmit Buffer */
+#define LP1_TXOUT_SHDW              0xFFC0111C         /* LP1 Shadow Output Transmit Buffer */
+#define LP2_CTL                     0xFFC01200         /* LP2 Control Register */
+#define LP2_STAT                    0xFFC01204         /* LP2 Status Register */
+#define LP2_DIV                     0xFFC01208         /* LP2 Clock Divider Value */
+#define LP2_CNT                     0xFFC0120C         /* LP2 Current Count Value of Clock Divider */
+#define LP2_TX                      0xFFC01210         /* LP2 Transmit Buffer */
+#define LP2_RX                      0xFFC01214         /* LP2 Receive Buffer */
+#define LP2_TXIN_SHDW               0xFFC01218         /* LP2 Shadow Input Transmit Buffer */
+#define LP2_TXOUT_SHDW              0xFFC0121C         /* LP2 Shadow Output Transmit Buffer */
+#define LP3_CTL                     0xFFC01300         /* LP3 Control Register */
+#define LP3_STAT                    0xFFC01304         /* LP3 Status Register */
+#define LP3_DIV                     0xFFC01308         /* LP3 Clock Divider Value */
+#define LP3_CNT                     0xFFC0130C         /* LP3 Current Count Value of Clock Divider */
+#define LP3_TX                      0xFFC01310         /* LP3 Transmit Buffer */
+#define LP3_RX                      0xFFC01314         /* LP3 Receive Buffer */
+#define LP3_TXIN_SHDW               0xFFC01318         /* LP3 Shadow Input Transmit Buffer */
+#define LP3_TXOUT_SHDW              0xFFC0131C         /* LP3 Shadow Output Transmit Buffer */
+#define TIMER0_REVID                0xFFC01400         /* TIMER0 Timer IP Version ID */
+#define TIMER0_RUN                  0xFFC01404         /* TIMER0 Timer Run Register */
+#define TIMER0_RUN_SET              0xFFC01408         /* TIMER0 Run Register Alias to Set */
+#define TIMER0_RUN_CLR              0xFFC0140C         /* TIMER0 Run Register Alias to Clear */
+#define TIMER0_STOP_CFG             0xFFC01410         /* TIMER0 Stop Config Register */
+#define TIMER0_STOP_CFG_SET         0xFFC01414         /* TIMER0 Stop Config Alias to Set */
+#define TIMER0_STOP_CFG_CLR         0xFFC01418         /* TIMER0 Stop Config Alias to Clear */
+#define TIMER0_DATA_IMSK            0xFFC0141C         /* TIMER0 Data Interrupt Mask register */
+#define TIMER0_STAT_IMSK            0xFFC01420         /* TIMER0 Status Interrupt Mask register */
+#define TIMER0_TRG_MSK              0xFFC01424         /* TIMER0 Output Trigger Mask register */
+#define TIMER0_TRG_IE               0xFFC01428         /* TIMER0 Slave Trigger Enable register */
+#define TIMER0_DATA_ILAT            0xFFC0142C         /* TIMER0 Data Interrupt Register */
+#define TIMER0_STAT_ILAT            0xFFC01430         /* TIMER0 Status (Error) Interrupt Register */
+#define TIMER0_ERR_TYPE             0xFFC01434         /* TIMER0 Register Indicating Type of Error */
+#define TIMER0_BCAST_PER            0xFFC01438         /* TIMER0 Broadcast Period */
+#define TIMER0_BCAST_WID            0xFFC0143C         /* TIMER0 Broadcast Width */
+#define TIMER0_BCAST_DLY            0xFFC01440         /* TIMER0 Broadcast Delay */
+#define TIMER0_TMR0_CFG             0xFFC01460         /* TIMER0 Per Timer Config Register */
+#define TIMER0_TMR1_CFG             0xFFC01480         /* TIMER0 Per Timer Config Register */
+#define TIMER0_TMR2_CFG             0xFFC014A0         /* TIMER0 Per Timer Config Register */
+#define TIMER0_TMR3_CFG             0xFFC014C0         /* TIMER0 Per Timer Config Register */
+#define TIMER0_TMR4_CFG             0xFFC014E0         /* TIMER0 Per Timer Config Register */
+#define TIMER0_TMR5_CFG             0xFFC01500         /* TIMER0 Per Timer Config Register */
+#define TIMER0_TMR6_CFG             0xFFC01520         /* TIMER0 Per Timer Config Register */
+#define TIMER0_TMR7_CFG             0xFFC01540         /* TIMER0 Per Timer Config Register */
+#define TIMER0_TMR0_CNT             0xFFC01464         /* TIMER0 Per Timer Counter Register */
+#define TIMER0_TMR1_CNT             0xFFC01484         /* TIMER0 Per Timer Counter Register */
+#define TIMER0_TMR2_CNT             0xFFC014A4         /* TIMER0 Per Timer Counter Register */
+#define TIMER0_TMR3_CNT             0xFFC014C4         /* TIMER0 Per Timer Counter Register */
+#define TIMER0_TMR4_CNT             0xFFC014E4         /* TIMER0 Per Timer Counter Register */
+#define TIMER0_TMR5_CNT             0xFFC01504         /* TIMER0 Per Timer Counter Register */
+#define TIMER0_TMR6_CNT             0xFFC01524         /* TIMER0 Per Timer Counter Register */
+#define TIMER0_TMR7_CNT             0xFFC01544         /* TIMER0 Per Timer Counter Register */
+#define TIMER0_TMR0_PER             0xFFC01468         /* TIMER0 Per Timer Period Register */
+#define TIMER0_TMR1_PER             0xFFC01488         /* TIMER0 Per Timer Period Register */
+#define TIMER0_TMR2_PER             0xFFC014A8         /* TIMER0 Per Timer Period Register */
+#define TIMER0_TMR3_PER             0xFFC014C8         /* TIMER0 Per Timer Period Register */
+#define TIMER0_TMR4_PER             0xFFC014E8         /* TIMER0 Per Timer Period Register */
+#define TIMER0_TMR5_PER             0xFFC01508         /* TIMER0 Per Timer Period Register */
+#define TIMER0_TMR6_PER             0xFFC01528         /* TIMER0 Per Timer Period Register */
+#define TIMER0_TMR7_PER             0xFFC01548         /* TIMER0 Per Timer Period Register */
+#define TIMER0_TMR0_WID             0xFFC0146C         /* TIMER0 Per Timer Width Register */
+#define TIMER0_TMR1_WID             0xFFC0148C         /* TIMER0 Per Timer Width Register */
+#define TIMER0_TMR2_WID             0xFFC014AC         /* TIMER0 Per Timer Width Register */
+#define TIMER0_TMR3_WID             0xFFC014CC         /* TIMER0 Per Timer Width Register */
+#define TIMER0_TMR4_WID             0xFFC014EC         /* TIMER0 Per Timer Width Register */
+#define TIMER0_TMR5_WID             0xFFC0150C         /* TIMER0 Per Timer Width Register */
+#define TIMER0_TMR6_WID             0xFFC0152C         /* TIMER0 Per Timer Width Register */
+#define TIMER0_TMR7_WID             0xFFC0154C         /* TIMER0 Per Timer Width Register */
+#define TIMER0_TMR0_DLY             0xFFC01470         /* TIMER0 Per Timer Delay Register */
+#define TIMER0_TMR1_DLY             0xFFC01490         /* TIMER0 Per Timer Delay Register */
+#define TIMER0_TMR2_DLY             0xFFC014B0         /* TIMER0 Per Timer Delay Register */
+#define TIMER0_TMR3_DLY             0xFFC014D0         /* TIMER0 Per Timer Delay Register */
+#define TIMER0_TMR4_DLY             0xFFC014F0         /* TIMER0 Per Timer Delay Register */
+#define TIMER0_TMR5_DLY             0xFFC01510         /* TIMER0 Per Timer Delay Register */
+#define TIMER0_TMR6_DLY             0xFFC01530         /* TIMER0 Per Timer Delay Register */
+#define TIMER0_TMR7_DLY             0xFFC01550         /* TIMER0 Per Timer Delay Register */
+#define CRC0_CTL                    0xFFC01C00         /* CRC0 Control Register */
+#define CRC0_DCNT                   0xFFC01C04         /* CRC0 Data Word Count Register */
+#define CRC0_DCNTRLD                0xFFC01C08         /* CRC0 Data Word Count Reload Register */
+#define CRC0_COMP                   0xFFC01C14         /* CRC0 DATA Compare Register */
+#define CRC0_FILLVAL                0xFFC01C18         /* CRC0 Fill Value Register */
+#define CRC0_DFIFO                  0xFFC01C1C         /* CRC0 DATA FIFO Register */
+#define CRC0_INEN                   0xFFC01C20         /* CRC0 Interrupt Enable Register */
+#define CRC0_INEN_SET               0xFFC01C24         /* CRC0 Interrupt Enable Set Register */
+#define CRC0_INEN_CLR               0xFFC01C28         /* CRC0 Interrupt Enable Clear Register */
+#define CRC0_POLY                   0xFFC01C2C         /* CRC0 Polynomial Register */
+#define CRC0_STAT                   0xFFC01C40         /* CRC0 Status Register */
+#define CRC0_DCNTCAP                0xFFC01C44         /* CRC0 DATA Count Capture Register */
+#define CRC0_RESULT_FIN             0xFFC01C4C         /* CRC0 Final CRC Result Register */
+#define CRC0_RESULT_CUR             0xFFC01C50         /* CRC0 Current CRC Result Register */
+#define CRC0_REVID                  0xFFC01C60         /* CRC0 Revision ID Register */
+#define CRC0_LUT0                   0xFFC01C84         /* CRC0 Look Up Table Register */
+#define CRC0_LUT1                   0xFFC01C88         /* CRC0 Look Up Table Register */
+#define CRC0_LUT2                   0xFFC01C8C         /* CRC0 Look Up Table Register */
+#define CRC0_LUT3                   0xFFC01C90         /* CRC0 Look Up Table Register */
+#define CRC0_LUT4                   0xFFC01C94         /* CRC0 Look Up Table Register */
+#define CRC0_LUT5                   0xFFC01C98         /* CRC0 Look Up Table Register */
+#define CRC0_LUT6                   0xFFC01C9C         /* CRC0 Look Up Table Register */
+#define CRC0_LUT7                   0xFFC01CA0         /* CRC0 Look Up Table Register */
+#define CRC0_LUT8                   0xFFC01CA4         /* CRC0 Look Up Table Register */
+#define CRC0_LUT9                   0xFFC01CA8         /* CRC0 Look Up Table Register */
+#define CRC0_LUT10                  0xFFC01CAC         /* CRC0 Look Up Table Register */
+#define CRC0_LUT11                  0xFFC01CB0         /* CRC0 Look Up Table Register */
+#define CRC0_LUT12                  0xFFC01CB4         /* CRC0 Look Up Table Register */
+#define CRC0_LUT13                  0xFFC01CB8         /* CRC0 Look Up Table Register */
+#define CRC0_LUT14                  0xFFC01CBC         /* CRC0 Look Up Table Register */
+#define CRC0_LUT15                  0xFFC01CC0         /* CRC0 Look Up Table Register */
+#define CRC1_CTL                    0xFFC01D00         /* CRC1 Control Register */
+#define CRC1_DCNT                   0xFFC01D04         /* CRC1 Data Word Count Register */
+#define CRC1_DCNTRLD                0xFFC01D08         /* CRC1 Data Word Count Reload Register */
+#define CRC1_COMP                   0xFFC01D14         /* CRC1 DATA Compare Register */
+#define CRC1_FILLVAL                0xFFC01D18         /* CRC1 Fill Value Register */
+#define CRC1_DFIFO                  0xFFC01D1C         /* CRC1 DATA FIFO Register */
+#define CRC1_INEN                   0xFFC01D20         /* CRC1 Interrupt Enable Register */
+#define CRC1_INEN_SET               0xFFC01D24         /* CRC1 Interrupt Enable Set Register */
+#define CRC1_INEN_CLR               0xFFC01D28         /* CRC1 Interrupt Enable Clear Register */
+#define CRC1_POLY                   0xFFC01D2C         /* CRC1 Polynomial Register */
+#define CRC1_STAT                   0xFFC01D40         /* CRC1 Status Register */
+#define CRC1_DCNTCAP                0xFFC01D44         /* CRC1 DATA Count Capture Register */
+#define CRC1_RESULT_FIN             0xFFC01D4C         /* CRC1 Final CRC Result Register */
+#define CRC1_RESULT_CUR             0xFFC01D50         /* CRC1 Current CRC Result Register */
+#define CRC1_REVID                  0xFFC01D60         /* CRC1 Revision ID Register */
+#define CRC1_LUT0                   0xFFC01D84         /* CRC1 Look Up Table Register */
+#define CRC1_LUT1                   0xFFC01D88         /* CRC1 Look Up Table Register */
+#define CRC1_LUT2                   0xFFC01D8C         /* CRC1 Look Up Table Register */
+#define CRC1_LUT3                   0xFFC01D90         /* CRC1 Look Up Table Register */
+#define CRC1_LUT4                   0xFFC01D94         /* CRC1 Look Up Table Register */
+#define CRC1_LUT5                   0xFFC01D98         /* CRC1 Look Up Table Register */
+#define CRC1_LUT6                   0xFFC01D9C         /* CRC1 Look Up Table Register */
+#define CRC1_LUT7                   0xFFC01DA0         /* CRC1 Look Up Table Register */
+#define CRC1_LUT8                   0xFFC01DA4         /* CRC1 Look Up Table Register */
+#define CRC1_LUT9                   0xFFC01DA8         /* CRC1 Look Up Table Register */
+#define CRC1_LUT10                  0xFFC01DAC         /* CRC1 Look Up Table Register */
+#define CRC1_LUT11                  0xFFC01DB0         /* CRC1 Look Up Table Register */
+#define CRC1_LUT12                  0xFFC01DB4         /* CRC1 Look Up Table Register */
+#define CRC1_LUT13                  0xFFC01DB8         /* CRC1 Look Up Table Register */
+#define CRC1_LUT14                  0xFFC01DBC         /* CRC1 Look Up Table Register */
+#define CRC1_LUT15                  0xFFC01DC0         /* CRC1 Look Up Table Register */
+#define TWI0_CLKDIV                 0xFFC01E00         /* TWI0 SCL Clock Divider */
+#define TWI0_CTL                    0xFFC01E04         /* TWI0 Control Register */
+#define TWI0_SLVCTL                 0xFFC01E08         /* TWI0 Slave Mode Control Register */
+#define TWI0_SLVSTAT                0xFFC01E0C         /* TWI0 Slave Mode Status Register */
+#define TWI0_SLVADDR                0xFFC01E10         /* TWI0 Slave Mode Address Register */
+#define TWI0_MSTRCTL                0xFFC01E14         /* TWI0 Master Mode Control Registers */
+#define TWI0_MSTRSTAT               0xFFC01E18         /* TWI0 Master Mode Status Register */
+#define TWI0_MSTRADDR               0xFFC01E1C         /* TWI0 Master Mode Address Register */
+#define TWI0_ISTAT                  0xFFC01E20         /* TWI0 Interrupt Status Register */
+#define TWI0_IMSK                   0xFFC01E24         /* TWI0 Interrupt Mask Register */
+#define TWI0_FIFOCTL                0xFFC01E28         /* TWI0 FIFO Control Register */
+#define TWI0_FIFOSTAT               0xFFC01E2C         /* TWI0 FIFO Status Register */
+#define TWI0_TXDATA8                0xFFC01E80         /* TWI0 FIFO Transmit Data Single-Byte Register */
+#define TWI0_TXDATA16               0xFFC01E84         /* TWI0 FIFO Transmit Data Double-Byte Register */
+#define TWI0_RXDATA8                0xFFC01E88         /* TWI0 FIFO Transmit Data Single-Byte Register */
+#define TWI0_RXDATA16               0xFFC01E8C         /* TWI0 FIFO Transmit Data Double-Byte Register */
+#define TWI1_CLKDIV                 0xFFC01F00         /* TWI1 SCL Clock Divider */
+#define TWI1_CTL                    0xFFC01F04         /* TWI1 Control Register */
+#define TWI1_SLVCTL                 0xFFC01F08         /* TWI1 Slave Mode Control Register */
+#define TWI1_SLVSTAT                0xFFC01F0C         /* TWI1 Slave Mode Status Register */
+#define TWI1_SLVADDR                0xFFC01F10         /* TWI1 Slave Mode Address Register */
+#define TWI1_MSTRCTL                0xFFC01F14         /* TWI1 Master Mode Control Registers */
+#define TWI1_MSTRSTAT               0xFFC01F18         /* TWI1 Master Mode Status Register */
+#define TWI1_MSTRADDR               0xFFC01F1C         /* TWI1 Master Mode Address Register */
+#define TWI1_ISTAT                  0xFFC01F20         /* TWI1 Interrupt Status Register */
+#define TWI1_IMSK                   0xFFC01F24         /* TWI1 Interrupt Mask Register */
+#define TWI1_FIFOCTL                0xFFC01F28         /* TWI1 FIFO Control Register */
+#define TWI1_FIFOSTAT               0xFFC01F2C         /* TWI1 FIFO Status Register */
+#define TWI1_TXDATA8                0xFFC01F80         /* TWI1 FIFO Transmit Data Single-Byte Register */
+#define TWI1_TXDATA16               0xFFC01F84         /* TWI1 FIFO Transmit Data Double-Byte Register */
+#define TWI1_RXDATA8                0xFFC01F88         /* TWI1 FIFO Transmit Data Single-Byte Register */
+#define TWI1_RXDATA16               0xFFC01F8C         /* TWI1 FIFO Transmit Data Double-Byte Register */
+#define UART0_REVID                 0xFFC02000         /* UART0 Revision ID Register */
+#define UART0_CTL                   0xFFC02004         /* UART0 Control Register */
+#define UART0_STAT                  0xFFC02008         /* UART0 Status Register */
+#define UART0_SCR                   0xFFC0200C         /* UART0 Scratch Register */
+#define UART0_CLK                   0xFFC02010         /* UART0 Clock Rate Register */
+#define UART0_IMSK                  0xFFC02014         /* UART0 Interrupt Mask Register */
+#define UART0_IMSK_SET              0xFFC02018         /* UART0 Interrupt Mask Set Register */
+#define UART0_IMSK_CLR              0xFFC0201C         /* UART0 Interrupt Mask Clear Register */
+#define UART0_RBR                   0xFFC02020         /* UART0 Receive Buffer Register */
+#define UART0_THR                   0xFFC02024         /* UART0 Transmit Hold Register */
+#define UART0_TAIP                  0xFFC02028         /* UART0 Transmit Address/Insert Pulse Register */
+#define UART0_TSR                   0xFFC0202C         /* UART0 Transmit Shift Register */
+#define UART0_RSR                   0xFFC02030         /* UART0 Receive Shift Register */
+#define UART0_TXCNT                 0xFFC02034         /* UART0 Transmit Counter Register */
+#define UART0_RXCNT                 0xFFC02038         /* UART0 Receive Counter Register */
+#define UART1_REVID                 0xFFC02400         /* UART1 Revision ID Register */
+#define UART1_CTL                   0xFFC02404         /* UART1 Control Register */
+#define UART1_STAT                  0xFFC02408         /* UART1 Status Register */
+#define UART1_SCR                   0xFFC0240C         /* UART1 Scratch Register */
+#define UART1_CLK                   0xFFC02410         /* UART1 Clock Rate Register */
+#define UART1_IMSK                  0xFFC02414         /* UART1 Interrupt Mask Register */
+#define UART1_IMSK_SET              0xFFC02418         /* UART1 Interrupt Mask Set Register */
+#define UART1_IMSK_CLR              0xFFC0241C         /* UART1 Interrupt Mask Clear Register */
+#define UART1_RBR                   0xFFC02420         /* UART1 Receive Buffer Register */
+#define UART1_THR                   0xFFC02424         /* UART1 Transmit Hold Register */
+#define UART1_TAIP                  0xFFC02428         /* UART1 Transmit Address/Insert Pulse Register */
+#define UART1_TSR                   0xFFC0242C         /* UART1 Transmit Shift Register */
+#define UART1_RSR                   0xFFC02430         /* UART1 Receive Shift Register */
+#define UART1_TXCNT                 0xFFC02434         /* UART1 Transmit Counter Register */
+#define UART1_RXCNT                 0xFFC02438         /* UART1 Receive Counter Register */
+#define PORTA_FER                   0xFFC03000         /* PORTA Port x Function Enable Register */
+#define PORTA_FER_SET               0xFFC03004         /* PORTA Port x Function Enable Set Register */
+#define PORTA_FER_CLR               0xFFC03008         /* PORTA Port x Function Enable Clear Register */
+#define PORTA_DATA                  0xFFC0300C         /* PORTA Port x GPIO Data Register */
+#define PORTA_DATA_SET              0xFFC03010         /* PORTA Port x GPIO Data Set Register */
+#define PORTA_DATA_CLR              0xFFC03014         /* PORTA Port x GPIO Data Clear Register */
+#define PORTA_DIR                   0xFFC03018         /* PORTA Port x GPIO Direction Register */
+#define PORTA_DIR_SET               0xFFC0301C         /* PORTA Port x GPIO Direction Set Register */
+#define PORTA_DIR_CLR               0xFFC03020         /* PORTA Port x GPIO Direction Clear Register */
+#define PORTA_INEN                  0xFFC03024         /* PORTA Port x GPIO Input Enable Register */
+#define PORTA_INEN_SET              0xFFC03028         /* PORTA Port x GPIO Input Enable Set Register */
+#define PORTA_INEN_CLR              0xFFC0302C         /* PORTA Port x GPIO Input Enable Clear Register */
+#define PORTA_MUX                   0xFFC03030         /* PORTA Port x Multiplexer Control Register */
+#define PORTA_DATA_TGL              0xFFC03034         /* PORTA Port x GPIO Input Enable Toggle Register */
+#define PORTA_POL                   0xFFC03038         /* PORTA Port x GPIO Programming Inversion Register */
+#define PORTA_POL_SET               0xFFC0303C         /* PORTA Port x GPIO Programming Inversion Set Register */
+#define PORTA_POL_CLR               0xFFC03040         /* PORTA Port x GPIO Programming Inversion Clear Register */
+#define PORTA_LOCK                  0xFFC03044         /* PORTA Port x GPIO Lock Register */
+#define PORTA_REVID                 0xFFC0307C         /* PORTA Port x GPIO Revision ID */
+#define PORTB_FER                   0xFFC03080         /* PORTB Port x Function Enable Register */
+#define PORTB_FER_SET               0xFFC03084         /* PORTB Port x Function Enable Set Register */
+#define PORTB_FER_CLR               0xFFC03088         /* PORTB Port x Function Enable Clear Register */
+#define PORTB_DATA                  0xFFC0308C         /* PORTB Port x GPIO Data Register */
+#define PORTB_DATA_SET              0xFFC03090         /* PORTB Port x GPIO Data Set Register */
+#define PORTB_DATA_CLR              0xFFC03094         /* PORTB Port x GPIO Data Clear Register */
+#define PORTB_DIR                   0xFFC03098         /* PORTB Port x GPIO Direction Register */
+#define PORTB_DIR_SET               0xFFC0309C         /* PORTB Port x GPIO Direction Set Register */
+#define PORTB_DIR_CLR               0xFFC030A0         /* PORTB Port x GPIO Direction Clear Register */
+#define PORTB_INEN                  0xFFC030A4         /* PORTB Port x GPIO Input Enable Register */
+#define PORTB_INEN_SET              0xFFC030A8         /* PORTB Port x GPIO Input Enable Set Register */
+#define PORTB_INEN_CLR              0xFFC030AC         /* PORTB Port x GPIO Input Enable Clear Register */
+#define PORTB_MUX                   0xFFC030B0         /* PORTB Port x Multiplexer Control Register */
+#define PORTB_DATA_TGL              0xFFC030B4         /* PORTB Port x GPIO Input Enable Toggle Register */
+#define PORTB_POL                   0xFFC030B8         /* PORTB Port x GPIO Programming Inversion Register */
+#define PORTB_POL_SET               0xFFC030BC         /* PORTB Port x GPIO Programming Inversion Set Register */
+#define PORTB_POL_CLR               0xFFC030C0         /* PORTB Port x GPIO Programming Inversion Clear Register */
+#define PORTB_LOCK                  0xFFC030C4         /* PORTB Port x GPIO Lock Register */
+#define PORTB_REVID                 0xFFC030FC         /* PORTB Port x GPIO Revision ID */
+#define PORTC_FER                   0xFFC03100         /* PORTC Port x Function Enable Register */
+#define PORTC_FER_SET               0xFFC03104         /* PORTC Port x Function Enable Set Register */
+#define PORTC_FER_CLR               0xFFC03108         /* PORTC Port x Function Enable Clear Register */
+#define PORTC_DATA                  0xFFC0310C         /* PORTC Port x GPIO Data Register */
+#define PORTC_DATA_SET              0xFFC03110         /* PORTC Port x GPIO Data Set Register */
+#define PORTC_DATA_CLR              0xFFC03114         /* PORTC Port x GPIO Data Clear Register */
+#define PORTC_DIR                   0xFFC03118         /* PORTC Port x GPIO Direction Register */
+#define PORTC_DIR_SET               0xFFC0311C         /* PORTC Port x GPIO Direction Set Register */
+#define PORTC_DIR_CLR               0xFFC03120         /* PORTC Port x GPIO Direction Clear Register */
+#define PORTC_INEN                  0xFFC03124         /* PORTC Port x GPIO Input Enable Register */
+#define PORTC_INEN_SET              0xFFC03128         /* PORTC Port x GPIO Input Enable Set Register */
+#define PORTC_INEN_CLR              0xFFC0312C         /* PORTC Port x GPIO Input Enable Clear Register */
+#define PORTC_MUX                   0xFFC03130         /* PORTC Port x Multiplexer Control Register */
+#define PORTC_DATA_TGL              0xFFC03134         /* PORTC Port x GPIO Input Enable Toggle Register */
+#define PORTC_POL                   0xFFC03138         /* PORTC Port x GPIO Programming Inversion Register */
+#define PORTC_POL_SET               0xFFC0313C         /* PORTC Port x GPIO Programming Inversion Set Register */
+#define PORTC_POL_CLR               0xFFC03140         /* PORTC Port x GPIO Programming Inversion Clear Register */
+#define PORTC_LOCK                  0xFFC03144         /* PORTC Port x GPIO Lock Register */
+#define PORTC_REVID                 0xFFC0317C         /* PORTC Port x GPIO Revision ID */
+#define PORTD_FER                   0xFFC03180         /* PORTD Port x Function Enable Register */
+#define PORTD_FER_SET               0xFFC03184         /* PORTD Port x Function Enable Set Register */
+#define PORTD_FER_CLR               0xFFC03188         /* PORTD Port x Function Enable Clear Register */
+#define PORTD_DATA                  0xFFC0318C         /* PORTD Port x GPIO Data Register */
+#define PORTD_DATA_SET              0xFFC03190         /* PORTD Port x GPIO Data Set Register */
+#define PORTD_DATA_CLR              0xFFC03194         /* PORTD Port x GPIO Data Clear Register */
+#define PORTD_DIR                   0xFFC03198         /* PORTD Port x GPIO Direction Register */
+#define PORTD_DIR_SET               0xFFC0319C         /* PORTD Port x GPIO Direction Set Register */
+#define PORTD_DIR_CLR               0xFFC031A0         /* PORTD Port x GPIO Direction Clear Register */
+#define PORTD_INEN                  0xFFC031A4         /* PORTD Port x GPIO Input Enable Register */
+#define PORTD_INEN_SET              0xFFC031A8         /* PORTD Port x GPIO Input Enable Set Register */
+#define PORTD_INEN_CLR              0xFFC031AC         /* PORTD Port x GPIO Input Enable Clear Register */
+#define PORTD_MUX                   0xFFC031B0         /* PORTD Port x Multiplexer Control Register */
+#define PORTD_DATA_TGL              0xFFC031B4         /* PORTD Port x GPIO Input Enable Toggle Register */
+#define PORTD_POL                   0xFFC031B8         /* PORTD Port x GPIO Programming Inversion Register */
+#define PORTD_POL_SET               0xFFC031BC         /* PORTD Port x GPIO Programming Inversion Set Register */
+#define PORTD_POL_CLR               0xFFC031C0         /* PORTD Port x GPIO Programming Inversion Clear Register */
+#define PORTD_LOCK                  0xFFC031C4         /* PORTD Port x GPIO Lock Register */
+#define PORTD_REVID                 0xFFC031FC         /* PORTD Port x GPIO Revision ID */
+#define PORTE_FER                   0xFFC03200         /* PORTE Port x Function Enable Register */
+#define PORTE_FER_SET               0xFFC03204         /* PORTE Port x Function Enable Set Register */
+#define PORTE_FER_CLR               0xFFC03208         /* PORTE Port x Function Enable Clear Register */
+#define PORTE_DATA                  0xFFC0320C         /* PORTE Port x GPIO Data Register */
+#define PORTE_DATA_SET              0xFFC03210         /* PORTE Port x GPIO Data Set Register */
+#define PORTE_DATA_CLR              0xFFC03214         /* PORTE Port x GPIO Data Clear Register */
+#define PORTE_DIR                   0xFFC03218         /* PORTE Port x GPIO Direction Register */
+#define PORTE_DIR_SET               0xFFC0321C         /* PORTE Port x GPIO Direction Set Register */
+#define PORTE_DIR_CLR               0xFFC03220         /* PORTE Port x GPIO Direction Clear Register */
+#define PORTE_INEN                  0xFFC03224         /* PORTE Port x GPIO Input Enable Register */
+#define PORTE_INEN_SET              0xFFC03228         /* PORTE Port x GPIO Input Enable Set Register */
+#define PORTE_INEN_CLR              0xFFC0322C         /* PORTE Port x GPIO Input Enable Clear Register */
+#define PORTE_MUX                   0xFFC03230         /* PORTE Port x Multiplexer Control Register */
+#define PORTE_DATA_TGL              0xFFC03234         /* PORTE Port x GPIO Input Enable Toggle Register */
+#define PORTE_POL                   0xFFC03238         /* PORTE Port x GPIO Programming Inversion Register */
+#define PORTE_POL_SET               0xFFC0323C         /* PORTE Port x GPIO Programming Inversion Set Register */
+#define PORTE_POL_CLR               0xFFC03240         /* PORTE Port x GPIO Programming Inversion Clear Register */
+#define PORTE_LOCK                  0xFFC03244         /* PORTE Port x GPIO Lock Register */
+#define PORTE_REVID                 0xFFC0327C         /* PORTE Port x GPIO Revision ID */
+#define PORTF_FER                   0xFFC03280         /* PORTF Port x Function Enable Register */
+#define PORTF_FER_SET               0xFFC03284         /* PORTF Port x Function Enable Set Register */
+#define PORTF_FER_CLR               0xFFC03288         /* PORTF Port x Function Enable Clear Register */
+#define PORTF_DATA                  0xFFC0328C         /* PORTF Port x GPIO Data Register */
+#define PORTF_DATA_SET              0xFFC03290         /* PORTF Port x GPIO Data Set Register */
+#define PORTF_DATA_CLR              0xFFC03294         /* PORTF Port x GPIO Data Clear Register */
+#define PORTF_DIR                   0xFFC03298         /* PORTF Port x GPIO Direction Register */
+#define PORTF_DIR_SET               0xFFC0329C         /* PORTF Port x GPIO Direction Set Register */
+#define PORTF_DIR_CLR               0xFFC032A0         /* PORTF Port x GPIO Direction Clear Register */
+#define PORTF_INEN                  0xFFC032A4         /* PORTF Port x GPIO Input Enable Register */
+#define PORTF_INEN_SET              0xFFC032A8         /* PORTF Port x GPIO Input Enable Set Register */
+#define PORTF_INEN_CLR              0xFFC032AC         /* PORTF Port x GPIO Input Enable Clear Register */
+#define PORTF_MUX                   0xFFC032B0         /* PORTF Port x Multiplexer Control Register */
+#define PORTF_DATA_TGL              0xFFC032B4         /* PORTF Port x GPIO Input Enable Toggle Register */
+#define PORTF_POL                   0xFFC032B8         /* PORTF Port x GPIO Programming Inversion Register */
+#define PORTF_POL_SET               0xFFC032BC         /* PORTF Port x GPIO Programming Inversion Set Register */
+#define PORTF_POL_CLR               0xFFC032C0         /* PORTF Port x GPIO Programming Inversion Clear Register */
+#define PORTF_LOCK                  0xFFC032C4         /* PORTF Port x GPIO Lock Register */
+#define PORTF_REVID                 0xFFC032FC         /* PORTF Port x GPIO Revision ID */
+#define PORTG_FER                   0xFFC03300         /* PORTG Port x Function Enable Register */
+#define PORTG_FER_SET               0xFFC03304         /* PORTG Port x Function Enable Set Register */
+#define PORTG_FER_CLR               0xFFC03308         /* PORTG Port x Function Enable Clear Register */
+#define PORTG_DATA                  0xFFC0330C         /* PORTG Port x GPIO Data Register */
+#define PORTG_DATA_SET              0xFFC03310         /* PORTG Port x GPIO Data Set Register */
+#define PORTG_DATA_CLR              0xFFC03314         /* PORTG Port x GPIO Data Clear Register */
+#define PORTG_DIR                   0xFFC03318         /* PORTG Port x GPIO Direction Register */
+#define PORTG_DIR_SET               0xFFC0331C         /* PORTG Port x GPIO Direction Set Register */
+#define PORTG_DIR_CLR               0xFFC03320         /* PORTG Port x GPIO Direction Clear Register */
+#define PORTG_INEN                  0xFFC03324         /* PORTG Port x GPIO Input Enable Register */
+#define PORTG_INEN_SET              0xFFC03328         /* PORTG Port x GPIO Input Enable Set Register */
+#define PORTG_INEN_CLR              0xFFC0332C         /* PORTG Port x GPIO Input Enable Clear Register */
+#define PORTG_MUX                   0xFFC03330         /* PORTG Port x Multiplexer Control Register */
+#define PORTG_DATA_TGL              0xFFC03334         /* PORTG Port x GPIO Input Enable Toggle Register */
+#define PORTG_POL                   0xFFC03338         /* PORTG Port x GPIO Programming Inversion Register */
+#define PORTG_POL_SET               0xFFC0333C         /* PORTG Port x GPIO Programming Inversion Set Register */
+#define PORTG_POL_CLR               0xFFC03340         /* PORTG Port x GPIO Programming Inversion Clear Register */
+#define PORTG_LOCK                  0xFFC03344         /* PORTG Port x GPIO Lock Register */
+#define PORTG_REVID                 0xFFC0337C         /* PORTG Port x GPIO Revision ID */
+#define PADS0_EMAC_PTP_CLKSEL       0xFFC03404         /* PADS0 Clock Selection for EMAC and PTP */
+#define PADS0_TWI_VSEL              0xFFC03408         /* PADS0 TWI Voltage Selection */
+#define PADS0_PORTS_DS              0xFFC03420         /* PADS0 Voltage Domain Control Register */
+#define PADS0_NONPORTS_DS           0xFFC03424         /* PADS0 Non-GPIO Drive Strength */
+#define PADS0_PORTS_HYST            0xFFC03440         /* PADS0 Hysteresis Enable Register */
+#define PINT0_MSK_SET               0xFFC04000         /* PINT0 Pint Mask Set Register */
+#define PINT0_MSK_CLR               0xFFC04004         /* PINT0 Pint Mask Clear Register */
+#define PINT0_REQ                   0xFFC04008         /* PINT0 Pint Request Register */
+#define PINT0_ASSIGN                0xFFC0400C         /* PINT0 Pint Assign Register */
+#define PINT0_EDGE_SET              0xFFC04010         /* PINT0 Pint Edge Set Register */
+#define PINT0_EDGE_CLR              0xFFC04014         /* PINT0 Pint Edge Clear Register */
+#define PINT0_INV_SET               0xFFC04018         /* PINT0 Pint Invert Set Register */
+#define PINT0_INV_CLR               0xFFC0401C         /* PINT0 Pint Invert Clear Register */
+#define PINT0_PINSTATE              0xFFC04020         /* PINT0 Pint Pinstate Register */
+#define PINT0_LATCH                 0xFFC04024         /* PINT0 Pint Latch Register */
+#define PINT1_MSK_SET               0xFFC04100         /* PINT1 Pint Mask Set Register */
+#define PINT1_MSK_CLR               0xFFC04104         /* PINT1 Pint Mask Clear Register */
+#define PINT1_REQ                   0xFFC04108         /* PINT1 Pint Request Register */
+#define PINT1_ASSIGN                0xFFC0410C         /* PINT1 Pint Assign Register */
+#define PINT1_EDGE_SET              0xFFC04110         /* PINT1 Pint Edge Set Register */
+#define PINT1_EDGE_CLR              0xFFC04114         /* PINT1 Pint Edge Clear Register */
+#define PINT1_INV_SET               0xFFC04118         /* PINT1 Pint Invert Set Register */
+#define PINT1_INV_CLR               0xFFC0411C         /* PINT1 Pint Invert Clear Register */
+#define PINT1_PINSTATE              0xFFC04120         /* PINT1 Pint Pinstate Register */
+#define PINT1_LATCH                 0xFFC04124         /* PINT1 Pint Latch Register */
+#define PINT2_MSK_SET               0xFFC04200         /* PINT2 Pint Mask Set Register */
+#define PINT2_MSK_CLR               0xFFC04204         /* PINT2 Pint Mask Clear Register */
+#define PINT2_REQ                   0xFFC04208         /* PINT2 Pint Request Register */
+#define PINT2_ASSIGN                0xFFC0420C         /* PINT2 Pint Assign Register */
+#define PINT2_EDGE_SET              0xFFC04210         /* PINT2 Pint Edge Set Register */
+#define PINT2_EDGE_CLR              0xFFC04214         /* PINT2 Pint Edge Clear Register */
+#define PINT2_INV_SET               0xFFC04218         /* PINT2 Pint Invert Set Register */
+#define PINT2_INV_CLR               0xFFC0421C         /* PINT2 Pint Invert Clear Register */
+#define PINT2_PINSTATE              0xFFC04220         /* PINT2 Pint Pinstate Register */
+#define PINT2_LATCH                 0xFFC04224         /* PINT2 Pint Latch Register */
+#define PINT3_MSK_SET               0xFFC04300         /* PINT3 Pint Mask Set Register */
+#define PINT3_MSK_CLR               0xFFC04304         /* PINT3 Pint Mask Clear Register */
+#define PINT3_REQ                   0xFFC04308         /* PINT3 Pint Request Register */
+#define PINT3_ASSIGN                0xFFC0430C         /* PINT3 Pint Assign Register */
+#define PINT3_EDGE_SET              0xFFC04310         /* PINT3 Pint Edge Set Register */
+#define PINT3_EDGE_CLR              0xFFC04314         /* PINT3 Pint Edge Clear Register */
+#define PINT3_INV_SET               0xFFC04318         /* PINT3 Pint Invert Set Register */
+#define PINT3_INV_CLR               0xFFC0431C         /* PINT3 Pint Invert Clear Register */
+#define PINT3_PINSTATE              0xFFC04320         /* PINT3 Pint Pinstate Register */
+#define PINT3_LATCH                 0xFFC04324         /* PINT3 Pint Latch Register */
+#define PINT4_MSK_SET               0xFFC04400         /* PINT4 Pint Mask Set Register */
+#define PINT4_MSK_CLR               0xFFC04404         /* PINT4 Pint Mask Clear Register */
+#define PINT4_REQ                   0xFFC04408         /* PINT4 Pint Request Register */
+#define PINT4_ASSIGN                0xFFC0440C         /* PINT4 Pint Assign Register */
+#define PINT4_EDGE_SET              0xFFC04410         /* PINT4 Pint Edge Set Register */
+#define PINT4_EDGE_CLR              0xFFC04414         /* PINT4 Pint Edge Clear Register */
+#define PINT4_INV_SET               0xFFC04418         /* PINT4 Pint Invert Set Register */
+#define PINT4_INV_CLR               0xFFC0441C         /* PINT4 Pint Invert Clear Register */
+#define PINT4_PINSTATE              0xFFC04420         /* PINT4 Pint Pinstate Register */
+#define PINT4_LATCH                 0xFFC04424         /* PINT4 Pint Latch Register */
+#define PINT5_MSK_SET               0xFFC04500         /* PINT5 Pint Mask Set Register */
+#define PINT5_MSK_CLR               0xFFC04504         /* PINT5 Pint Mask Clear Register */
+#define PINT5_REQ                   0xFFC04508         /* PINT5 Pint Request Register */
+#define PINT5_ASSIGN                0xFFC0450C         /* PINT5 Pint Assign Register */
+#define PINT5_EDGE_SET              0xFFC04510         /* PINT5 Pint Edge Set Register */
+#define PINT5_EDGE_CLR              0xFFC04514         /* PINT5 Pint Edge Clear Register */
+#define PINT5_INV_SET               0xFFC04518         /* PINT5 Pint Invert Set Register */
+#define PINT5_INV_CLR               0xFFC0451C         /* PINT5 Pint Invert Clear Register */
+#define PINT5_PINSTATE              0xFFC04520         /* PINT5 Pint Pinstate Register */
+#define PINT5_LATCH                 0xFFC04524         /* PINT5 Pint Latch Register */
+#define SMC_GCTL                   0xFFC16004         /* SMC0 SMC Control Register */
+#define SMC_GSTAT                  0xFFC16008         /* SMC0 SMC Status Register */
+#define SMC_B0CTL                  0xFFC1600C         /* SMC0 SMC Bank0 Control Register */
+#define SMC_B0TIM                  0xFFC16010         /* SMC0 SMC Bank0 Timing Register */
+#define SMC_B0ETIM                 0xFFC16014         /* SMC0 SMC Bank0 Extended Timing Register */
+#define SMC_B1CTL                  0xFFC1601C         /* SMC0 SMC BANK1 Control Register */
+#define SMC_B1TIM                  0xFFC16020         /* SMC0 SMC BANK1 Timing Register */
+#define SMC_B1ETIM                 0xFFC16024         /* SMC0 SMC BANK1 Extended Timing Register */
+#define SMC_B2CTL                  0xFFC1602C         /* SMC0 SMC BANK2 Control Register */
+#define SMC_B2TIM                  0xFFC16030         /* SMC0 SMC BANK2 Timing Register */
+#define SMC_B2ETIM                 0xFFC16034         /* SMC0 SMC BANK2 Extended Timing Register */
+#define SMC_B3CTL                  0xFFC1603C         /* SMC0 SMC BANK3 Control Register */
+#define SMC_B3TIM                  0xFFC16040         /* SMC0 SMC BANK3 Timing Register */
+#define SMC_B3ETIM                 0xFFC16044         /* SMC0 SMC BANK3 Extended Timing Register */
+#define WDOG_CTL                   0xFFC17000         /* WDOG0 Control Register */
+#define WDOG_CNT                   0xFFC17004         /* WDOG0 Count Register */
+#define WDOG_STAT                  0xFFC17008         /* WDOG0 Watchdog Timer Status Register */
+#define WDOG1_CTL                   0xFFC17800         /* WDOG1 Control Register */
+#define WDOG1_CNT                   0xFFC17804         /* WDOG1 Count Register */
+#define WDOG1_STAT                  0xFFC17808         /* WDOG1 Watchdog Timer Status Register */
+#define EPPI0_STAT                  0xFFC18000         /* EPPI0 Status Register */
+#define EPPI0_HCNT                  0xFFC18004         /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDLY                  0xFFC18008         /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCNT                  0xFFC1800C         /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDLY                  0xFFC18010         /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME                 0xFFC18014         /* EPPI0 Lines Per Frame Register */
+#define EPPI0_LINE                  0xFFC18018         /* EPPI0 Samples Per Line Register */
+#define EPPI0_CLKDIV                0xFFC1801C         /* EPPI0 Clock Divide Register */
+#define EPPI0_CTL                   0xFFC18020         /* EPPI0 Control Register */
+#define EPPI0_FS1_WLHB              0xFFC18024         /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1_PASPL             0xFFC18028         /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
+#define EPPI0_FS2_WLVB              0xFFC1802C         /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
+#define EPPI0_FS2_PALPF             0xFFC18030         /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
+#define EPPI0_IMSK                  0xFFC18034         /* EPPI0 Interrupt Mask Register */
+#define EPPI0_ODDCLIP               0xFFC1803C         /* EPPI0 Clipping Register for ODD (Chroma) Data */
+#define EPPI0_EVENCLIP              0xFFC18040         /* EPPI0 Clipping Register for EVEN (Luma) Data */
+#define EPPI0_FS1_DLY               0xFFC18044         /* EPPI0 Frame Sync 1 Delay Value */
+#define EPPI0_FS2_DLY               0xFFC18048         /* EPPI0 Frame Sync 2 Delay Value */
+#define EPPI0_CTL2                  0xFFC1804C         /* EPPI0 Control Register 2 */
+#define EPPI1_STAT                  0xFFC18400         /* EPPI1 Status Register */
+#define EPPI1_HCNT                  0xFFC18404         /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDLY                  0xFFC18408         /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCNT                  0xFFC1840C         /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDLY                  0xFFC18410         /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                 0xFFC18414         /* EPPI1 Lines Per Frame Register */
+#define EPPI1_LINE                  0xFFC18418         /* EPPI1 Samples Per Line Register */
+#define EPPI1_CLKDIV                0xFFC1841C         /* EPPI1 Clock Divide Register */
+#define EPPI1_CTL                   0xFFC18420         /* EPPI1 Control Register */
+#define EPPI1_FS1_WLHB              0xFFC18424         /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1_PASPL             0xFFC18428         /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
+#define EPPI1_FS2_WLVB              0xFFC1842C         /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
+#define EPPI1_FS2_PALPF             0xFFC18430         /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
+#define EPPI1_IMSK                  0xFFC18434         /* EPPI1 Interrupt Mask Register */
+#define EPPI1_ODDCLIP               0xFFC1843C         /* EPPI1 Clipping Register for ODD (Chroma) Data */
+#define EPPI1_EVENCLIP              0xFFC18440         /* EPPI1 Clipping Register for EVEN (Luma) Data */
+#define EPPI1_FS1_DLY               0xFFC18444         /* EPPI1 Frame Sync 1 Delay Value */
+#define EPPI1_FS2_DLY               0xFFC18448         /* EPPI1 Frame Sync 2 Delay Value */
+#define EPPI1_CTL2                  0xFFC1844C         /* EPPI1 Control Register 2 */
+#define EPPI2_STAT                  0xFFC18800         /* EPPI2 Status Register */
+#define EPPI2_HCNT                  0xFFC18804         /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDLY                  0xFFC18808         /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCNT                  0xFFC1880C         /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDLY                  0xFFC18810         /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                 0xFFC18814         /* EPPI2 Lines Per Frame Register */
+#define EPPI2_LINE                  0xFFC18818         /* EPPI2 Samples Per Line Register */
+#define EPPI2_CLKDIV                0xFFC1881C         /* EPPI2 Clock Divide Register */
+#define EPPI2_CTL                   0xFFC18820         /* EPPI2 Control Register */
+#define EPPI2_FS1_WLHB              0xFFC18824         /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1_PASPL             0xFFC18828         /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
+#define EPPI2_FS2_WLVB              0xFFC1882C         /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
+#define EPPI2_FS2_PALPF             0xFFC18830         /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
+#define EPPI2_IMSK                  0xFFC18834         /* EPPI2 Interrupt Mask Register */
+#define EPPI2_ODDCLIP               0xFFC1883C         /* EPPI2 Clipping Register for ODD (Chroma) Data */
+#define EPPI2_EVENCLIP              0xFFC18840         /* EPPI2 Clipping Register for EVEN (Luma) Data */
+#define EPPI2_FS1_DLY               0xFFC18844         /* EPPI2 Frame Sync 1 Delay Value */
+#define EPPI2_FS2_DLY               0xFFC18848         /* EPPI2 Frame Sync 2 Delay Value */
+#define EPPI2_CTL2                  0xFFC1884C         /* EPPI2 Control Register 2 */
+#define PIXC0_CTL                   0xFFC19000         /* PIXC0 Control Register */
+#define PIXC0_PPL                   0xFFC19004         /* PIXC0 Pixels Per Line Register */
+#define PIXC0_LPF                   0xFFC19008         /* PIXC0 Line Per Frame Register */
+#define PIXC0_HSTART_A              0xFFC1900C         /* PIXC0 Overlay A Horizontal Start Register */
+#define PIXC0_HEND_A                0xFFC19010         /* PIXC0 Overlay A Horizontal End Register */
+#define PIXC0_VSTART_A              0xFFC19014         /* PIXC0 Overlay A Vertical Start Register */
+#define PIXC0_VEND_A                0xFFC19018         /* PIXC0 Overlay A Vertical End Register */
+#define PIXC0_TRANSP_A              0xFFC1901C         /* PIXC0 Overlay A Transparency Ratio Register */
+#define PIXC0_HSTART_B              0xFFC19020         /* PIXC0 Overlay B Horizontal Start Register */
+#define PIXC0_HEND_B                0xFFC19024         /* PIXC0 Overlay B Horizontal End Register */
+#define PIXC0_VSTART_B              0xFFC19028         /* PIXC0 Overlay B Vertical Start Register */
+#define PIXC0_VEND_B                0xFFC1902C         /* PIXC0 Overlay B Vertical End Register */
+#define PIXC0_TRANSP_B              0xFFC19030         /* PIXC0 Overlay B Transparency Ratio Register */
+#define PIXC0_IRQSTAT               0xFFC1903C         /* PIXC0 Interrupt Status Register */
+#define PIXC0_CONRY                 0xFFC19040         /* PIXC0 RY Conversion Component Register */
+#define PIXC0_CONGU                 0xFFC19044         /* PIXC0 GU Conversion Component Register */
+#define PIXC0_CONBV                 0xFFC19048         /* PIXC0 BV Conversion Component Register */
+#define PIXC0_CCBIAS                0xFFC1904C         /* PIXC0 Conversion Bias Register */
+#define PIXC0_TC                    0xFFC19050         /* PIXC0 Transparency Register */
+#define PIXC0_REVID                 0xFFC19054         /* PIXC0 PIXC Revision Id */
+#define PVP0_REVID                  0xFFC1A000         /* PVP0 Revision ID */
+#define PVP0_CTL                    0xFFC1A004         /* PVP0 Control */
+#define PVP0_IMSK0                  0xFFC1A008         /* PVP0 INTn interrupt line masks */
+#define PVP0_IMSK1                  0xFFC1A00C         /* PVP0 INTn interrupt line masks */
+#define PVP0_STAT                   0xFFC1A010         /* PVP0 Status */
+#define PVP0_ILAT                   0xFFC1A014         /* PVP0 Latched status */
+#define PVP0_IREQ0                  0xFFC1A018         /* PVP0 INT0 masked latched status */
+#define PVP0_IREQ1                  0xFFC1A01C         /* PVP0 INT0 masked latched status */
+#define PVP0_OPF0_CFG               0xFFC1A020         /* PVP0 Config */
+#define PVP0_OPF1_CFG               0xFFC1A040         /* PVP0 Config */
+#define PVP0_OPF2_CFG               0xFFC1A060         /* PVP0 Config */
+#define PVP0_OPF0_CTL               0xFFC1A024         /* PVP0 Control */
+#define PVP0_OPF1_CTL               0xFFC1A044         /* PVP0 Control */
+#define PVP0_OPF2_CTL               0xFFC1A064         /* PVP0 Control */
+#define PVP0_OPF3_CFG               0xFFC1A080         /* PVP0 Config */
+#define PVP0_OPF3_CTL               0xFFC1A084         /* PVP0 Control */
+#define PVP0_PEC_CFG                0xFFC1A0A0         /* PVP0 Config */
+#define PVP0_PEC_CTL                0xFFC1A0A4         /* PVP0 Control */
+#define PVP0_PEC_D1TH0              0xFFC1A0A8         /* PVP0 Lower Hysteresis Threshold */
+#define PVP0_PEC_D1TH1              0xFFC1A0AC         /* PVP0 Upper Hysteresis Threshold */
+#define PVP0_PEC_D2TH0              0xFFC1A0B0         /* PVP0 Weak Zero Crossing Threshold */
+#define PVP0_PEC_D2TH1              0xFFC1A0B4         /* PVP0 Strong Zero Crossing Threshold */
+#define PVP0_IIM0_CFG               0xFFC1A0C0         /* PVP0 Config */
+#define PVP0_IIM1_CFG               0xFFC1A0E0         /* PVP0 Config */
+#define PVP0_IIM0_CTL               0xFFC1A0C4         /* PVP0 Control */
+#define PVP0_IIM1_CTL               0xFFC1A0E4         /* PVP0 Control */
+#define PVP0_IIM0_SCALE             0xFFC1A0C8         /* PVP0 Scaler Values */
+#define PVP0_IIM1_SCALE             0xFFC1A0E8         /* PVP0 Scaler Values */
+#define PVP0_IIM0_SOVF_STAT         0xFFC1A0CC         /* PVP0 Signed Overflow Status */
+#define PVP0_IIM1_SOVF_STAT         0xFFC1A0EC         /* PVP0 Signed Overflow Status */
+#define PVP0_IIM0_UOVF_STAT         0xFFC1A0D0         /* PVP0 Unsigned Overflow Status */
+#define PVP0_IIM1_UOVF_STAT         0xFFC1A0F0         /* PVP0 Unsigned Overflow Status */
+#define PVP0_ACU_CFG                0xFFC1A100         /* PVP0 ACU Configuration Register */
+#define PVP0_ACU_CTL                0xFFC1A104         /* PVP0 ACU Control Register */
+#define PVP0_ACU_OFFSET             0xFFC1A108         /* PVP0 SUM constant register */
+#define PVP0_ACU_FACTOR             0xFFC1A10C         /* PVP0 PROD constant register */
+#define PVP0_ACU_SHIFT              0xFFC1A110         /* PVP0 Shift constant register */
+#define PVP0_ACU_MIN                0xFFC1A114         /* PVP0 Lower saturation threshold set to MIN */
+#define PVP0_ACU_MAX                0xFFC1A118         /* PVP0 Upper saturation threshold set to MAX */
+#define PVP0_UDS_CFG                0xFFC1A140         /* PVP0 UDS Configuration Register */
+#define PVP0_UDS_CTL                0xFFC1A144         /* PVP0 UDS Control Register */
+#define PVP0_UDS_OHCNT              0xFFC1A148         /* PVP0 UDS Output H Dimension */
+#define PVP0_UDS_OVCNT              0xFFC1A14C         /* PVP0 UDS Output V Dimension */
+#define PVP0_UDS_HAVG               0xFFC1A150         /* PVP0 UDS H Taps */
+#define PVP0_UDS_VAVG               0xFFC1A154         /* PVP0 UDS V Taps */
+#define PVP0_IPF0_CFG               0xFFC1A180         /* PVP0 Configuration */
+#define PVP0_IPF0_PIPECTL           0xFFC1A184         /* PVP0 Pipe Control */
+#define PVP0_IPF1_PIPECTL           0xFFC1A1C4         /* PVP0 Pipe Control */
+#define PVP0_IPF0_CTL               0xFFC1A188         /* PVP0 Control */
+#define PVP0_IPF1_CTL               0xFFC1A1C8         /* PVP0 Control */
+#define PVP0_IPF0_TAG               0xFFC1A18C         /* PVP0 TAG Value */
+#define PVP0_IPF1_TAG               0xFFC1A1CC         /* PVP0 TAG Value */
+#define PVP0_IPF0_FCNT              0xFFC1A190         /* PVP0 Frame Count */
+#define PVP0_IPF1_FCNT              0xFFC1A1D0         /* PVP0 Frame Count */
+#define PVP0_IPF0_HCNT              0xFFC1A194         /* PVP0 Horizontal Count */
+#define PVP0_IPF1_HCNT              0xFFC1A1D4         /* PVP0 Horizontal Count */
+#define PVP0_IPF0_VCNT              0xFFC1A198         /* PVP0 Vertical Count */
+#define PVP0_IPF1_VCNT              0xFFC1A1D8         /* PVP0 Vertical Count */
+#define PVP0_IPF0_HPOS              0xFFC1A19C         /* PVP0 Horizontal Position */
+#define PVP0_IPF0_VPOS              0xFFC1A1A0         /* PVP0 Vertical Position */
+#define PVP0_IPF0_TAG_STAT          0xFFC1A1A4         /* PVP0 TAG Status */
+#define PVP0_IPF1_TAG_STAT          0xFFC1A1E4         /* PVP0 TAG Status */
+#define PVP0_IPF1_CFG               0xFFC1A1C0         /* PVP0 Configuration */
+#define PVP0_CNV0_CFG               0xFFC1A200         /* PVP0 Configuration */
+#define PVP0_CNV1_CFG               0xFFC1A280         /* PVP0 Configuration */
+#define PVP0_CNV2_CFG               0xFFC1A300         /* PVP0 Configuration */
+#define PVP0_CNV3_CFG               0xFFC1A380         /* PVP0 Configuration */
+#define PVP0_CNV0_CTL               0xFFC1A204         /* PVP0 Control */
+#define PVP0_CNV1_CTL               0xFFC1A284         /* PVP0 Control */
+#define PVP0_CNV2_CTL               0xFFC1A304         /* PVP0 Control */
+#define PVP0_CNV3_CTL               0xFFC1A384         /* PVP0 Control */
+#define PVP0_CNV0_C00C01            0xFFC1A208         /* PVP0 Coefficients 0, 0 and 0, 1 */
+#define PVP0_CNV1_C00C01            0xFFC1A288         /* PVP0 Coefficients 0, 0 and 0, 1 */
+#define PVP0_CNV2_C00C01            0xFFC1A308         /* PVP0 Coefficients 0, 0 and 0, 1 */
+#define PVP0_CNV3_C00C01            0xFFC1A388         /* PVP0 Coefficients 0, 0 and 0, 1 */
+#define PVP0_CNV0_C02C03            0xFFC1A20C         /* PVP0 Coefficients 0, 2 and 0, 3 */
+#define PVP0_CNV1_C02C03            0xFFC1A28C         /* PVP0 Coefficients 0, 2 and 0, 3 */
+#define PVP0_CNV2_C02C03            0xFFC1A30C         /* PVP0 Coefficients 0, 2 and 0, 3 */
+#define PVP0_CNV3_C02C03            0xFFC1A38C         /* PVP0 Coefficients 0, 2 and 0, 3 */
+#define PVP0_CNV0_C04               0xFFC1A210         /* PVP0 Coefficient 0, 4 */
+#define PVP0_CNV1_C04               0xFFC1A290         /* PVP0 Coefficient 0, 4 */
+#define PVP0_CNV2_C04               0xFFC1A310         /* PVP0 Coefficient 0, 4 */
+#define PVP0_CNV3_C04               0xFFC1A390         /* PVP0 Coefficient 0, 4 */
+#define PVP0_CNV0_C10C11            0xFFC1A214         /* PVP0 Coefficients 1, 0 and 1, 1 */
+#define PVP0_CNV1_C10C11            0xFFC1A294         /* PVP0 Coefficients 1, 0 and 1, 1 */
+#define PVP0_CNV2_C10C11            0xFFC1A314         /* PVP0 Coefficients 1, 0 and 1, 1 */
+#define PVP0_CNV3_C10C11            0xFFC1A394         /* PVP0 Coefficients 1, 0 and 1, 1 */
+#define PVP0_CNV0_C12C13            0xFFC1A218         /* PVP0 Coefficients 1, 2 and 1, 3 */
+#define PVP0_CNV1_C12C13            0xFFC1A298         /* PVP0 Coefficients 1, 2 and 1, 3 */
+#define PVP0_CNV2_C12C13            0xFFC1A318         /* PVP0 Coefficients 1, 2 and 1, 3 */
+#define PVP0_CNV3_C12C13            0xFFC1A398         /* PVP0 Coefficients 1, 2 and 1, 3 */
+#define PVP0_CNV0_C14               0xFFC1A21C         /* PVP0 Coefficient 1, 4 */
+#define PVP0_CNV1_C14               0xFFC1A29C         /* PVP0 Coefficient 1, 4 */
+#define PVP0_CNV2_C14               0xFFC1A31C         /* PVP0 Coefficient 1, 4 */
+#define PVP0_CNV3_C14               0xFFC1A39C         /* PVP0 Coefficient 1, 4 */
+#define PVP0_CNV0_C20C21            0xFFC1A220         /* PVP0 Coefficients 2, 0 and 2, 1 */
+#define PVP0_CNV1_C20C21            0xFFC1A2A0         /* PVP0 Coefficients 2, 0 and 2, 1 */
+#define PVP0_CNV2_C20C21            0xFFC1A320         /* PVP0 Coefficients 2, 0 and 2, 1 */
+#define PVP0_CNV3_C20C21            0xFFC1A3A0         /* PVP0 Coefficients 2, 0 and 2, 1 */
+#define PVP0_CNV0_C22C23            0xFFC1A224         /* PVP0 Coefficients 2, 2 and 2, 3 */
+#define PVP0_CNV1_C22C23            0xFFC1A2A4         /* PVP0 Coefficients 2, 2 and 2, 3 */
+#define PVP0_CNV2_C22C23            0xFFC1A324         /* PVP0 Coefficients 2, 2 and 2, 3 */
+#define PVP0_CNV3_C22C23            0xFFC1A3A4         /* PVP0 Coefficients 2, 2 and 2, 3 */
+#define PVP0_CNV0_C24               0xFFC1A228         /* PVP0 Coefficient 2,4 */
+#define PVP0_CNV1_C24               0xFFC1A2A8         /* PVP0 Coefficient 2,4 */
+#define PVP0_CNV2_C24               0xFFC1A328         /* PVP0 Coefficient 2,4 */
+#define PVP0_CNV3_C24               0xFFC1A3A8         /* PVP0 Coefficient 2,4 */
+#define PVP0_CNV0_C30C31            0xFFC1A22C         /* PVP0 Coefficients 3, 0 and 3, 1 */
+#define PVP0_CNV1_C30C31            0xFFC1A2AC         /* PVP0 Coefficients 3, 0 and 3, 1 */
+#define PVP0_CNV2_C30C31            0xFFC1A32C         /* PVP0 Coefficients 3, 0 and 3, 1 */
+#define PVP0_CNV3_C30C31            0xFFC1A3AC         /* PVP0 Coefficients 3, 0 and 3, 1 */
+#define PVP0_CNV0_C32C33            0xFFC1A230         /* PVP0 Coefficients 3, 2 and 3, 3 */
+#define PVP0_CNV1_C32C33            0xFFC1A2B0         /* PVP0 Coefficients 3, 2 and 3, 3 */
+#define PVP0_CNV2_C32C33            0xFFC1A330         /* PVP0 Coefficients 3, 2 and 3, 3 */
+#define PVP0_CNV3_C32C33            0xFFC1A3B0         /* PVP0 Coefficients 3, 2 and 3, 3 */
+#define PVP0_CNV0_C34               0xFFC1A234         /* PVP0 Coefficient 3, 4 */
+#define PVP0_CNV1_C34               0xFFC1A2B4         /* PVP0 Coefficient 3, 4 */
+#define PVP0_CNV2_C34               0xFFC1A334         /* PVP0 Coefficient 3, 4 */
+#define PVP0_CNV3_C34               0xFFC1A3B4         /* PVP0 Coefficient 3, 4 */
+#define PVP0_CNV0_C40C41            0xFFC1A238         /* PVP0 Coefficients 4, 0 and 4, 1 */
+#define PVP0_CNV1_C40C41            0xFFC1A2B8         /* PVP0 Coefficients 4, 0 and 4, 1 */
+#define PVP0_CNV2_C40C41            0xFFC1A338         /* PVP0 Coefficients 4, 0 and 4, 1 */
+#define PVP0_CNV3_C40C41            0xFFC1A3B8         /* PVP0 Coefficients 4, 0 and 4, 1 */
+#define PVP0_CNV0_C42C43            0xFFC1A23C         /* PVP0 Coefficients 4, 2 and 4, 3 */
+#define PVP0_CNV1_C42C43            0xFFC1A2BC         /* PVP0 Coefficients 4, 2 and 4, 3 */
+#define PVP0_CNV2_C42C43            0xFFC1A33C         /* PVP0 Coefficients 4, 2 and 4, 3 */
+#define PVP0_CNV3_C42C43            0xFFC1A3BC         /* PVP0 Coefficients 4, 2 and 4, 3 */
+#define PVP0_CNV0_C44               0xFFC1A240         /* PVP0 Coefficient 4, 4 */
+#define PVP0_CNV1_C44               0xFFC1A2C0         /* PVP0 Coefficient 4, 4 */
+#define PVP0_CNV2_C44               0xFFC1A340         /* PVP0 Coefficient 4, 4 */
+#define PVP0_CNV3_C44               0xFFC1A3C0         /* PVP0 Coefficient 4, 4 */
+#define PVP0_CNV0_SCALE             0xFFC1A244         /* PVP0 Scaling factor */
+#define PVP0_CNV1_SCALE             0xFFC1A2C4         /* PVP0 Scaling factor */
+#define PVP0_CNV2_SCALE             0xFFC1A344         /* PVP0 Scaling factor */
+#define PVP0_CNV3_SCALE             0xFFC1A3C4         /* PVP0 Scaling factor */
+#define PVP0_THC0_CFG               0xFFC1A400         /* PVP0 Configuration */
+#define PVP0_THC1_CFG               0xFFC1A500         /* PVP0 Configuration */
+#define PVP0_THC0_CTL               0xFFC1A404         /* PVP0 Control */
+#define PVP0_THC1_CTL               0xFFC1A504         /* PVP0 Control */
+#define PVP0_THC0_HFCNT             0xFFC1A408         /* PVP0 Number of frames */
+#define PVP0_THC1_HFCNT             0xFFC1A508         /* PVP0 Number of frames */
+#define PVP0_THC0_RMAXREP           0xFFC1A40C         /* PVP0 Maximum number of RLE reports */
+#define PVP0_THC1_RMAXREP           0xFFC1A50C         /* PVP0 Maximum number of RLE reports */
+#define PVP0_THC0_CMINVAL           0xFFC1A410         /* PVP0 Min clip value */
+#define PVP0_THC1_CMINVAL           0xFFC1A510         /* PVP0 Min clip value */
+#define PVP0_THC0_CMINTH            0xFFC1A414         /* PVP0 Clip Min Threshold */
+#define PVP0_THC1_CMINTH            0xFFC1A514         /* PVP0 Clip Min Threshold */
+#define PVP0_THC0_CMAXTH            0xFFC1A418         /* PVP0 Clip Max Threshold */
+#define PVP0_THC1_CMAXTH            0xFFC1A518         /* PVP0 Clip Max Threshold */
+#define PVP0_THC0_CMAXVAL           0xFFC1A41C         /* PVP0 Max clip value */
+#define PVP0_THC1_CMAXVAL           0xFFC1A51C         /* PVP0 Max clip value */
+#define PVP0_THC0_TH0               0xFFC1A420         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH0               0xFFC1A520         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH1               0xFFC1A424         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH1               0xFFC1A524         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH2               0xFFC1A428         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH2               0xFFC1A528         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH3               0xFFC1A42C         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH3               0xFFC1A52C         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH4               0xFFC1A430         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH4               0xFFC1A530         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH5               0xFFC1A434         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH5               0xFFC1A534         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH6               0xFFC1A438         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH6               0xFFC1A538         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH7               0xFFC1A43C         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH7               0xFFC1A53C         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH8               0xFFC1A440         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH8               0xFFC1A540         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH9               0xFFC1A444         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH9               0xFFC1A544         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH10              0xFFC1A448         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH10              0xFFC1A548         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH11              0xFFC1A44C         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH11              0xFFC1A54C         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH12              0xFFC1A450         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH12              0xFFC1A550         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH13              0xFFC1A454         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH13              0xFFC1A554         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH14              0xFFC1A458         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH14              0xFFC1A558         /* PVP0 Threshold Value */
+#define PVP0_THC0_TH15              0xFFC1A45C         /* PVP0 Threshold Value */
+#define PVP0_THC1_TH15              0xFFC1A55C         /* PVP0 Threshold Value */
+#define PVP0_THC0_HHPOS             0xFFC1A460         /* PVP0 Window start X-coordinate */
+#define PVP0_THC1_HHPOS             0xFFC1A560         /* PVP0 Window start X-coordinate */
+#define PVP0_THC0_HVPOS             0xFFC1A464         /* PVP0 Window start Y-coordinate */
+#define PVP0_THC1_HVPOS             0xFFC1A564         /* PVP0 Window start Y-coordinate */
+#define PVP0_THC0_HHCNT             0xFFC1A468         /* PVP0 Window width in X dimension */
+#define PVP0_THC1_HHCNT             0xFFC1A568         /* PVP0 Window width in X dimension */
+#define PVP0_THC0_HVCNT             0xFFC1A46C         /* PVP0 Window width in Y dimension */
+#define PVP0_THC1_HVCNT             0xFFC1A56C         /* PVP0 Window width in Y dimension */
+#define PVP0_THC0_RHPOS             0xFFC1A470         /* PVP0 Window start X-coordinate */
+#define PVP0_THC1_RHPOS             0xFFC1A570         /* PVP0 Window start X-coordinate */
+#define PVP0_THC0_RVPOS             0xFFC1A474         /* PVP0 Window start Y-coordinate */
+#define PVP0_THC1_RVPOS             0xFFC1A574         /* PVP0 Window start Y-coordinate */
+#define PVP0_THC0_RHCNT             0xFFC1A478         /* PVP0 Window width in X dimension */
+#define PVP0_THC1_RHCNT             0xFFC1A578         /* PVP0 Window width in X dimension */
+#define PVP0_THC0_RVCNT             0xFFC1A47C         /* PVP0 Window width in Y dimension */
+#define PVP0_THC1_RVCNT             0xFFC1A57C         /* PVP0 Window width in Y dimension */
+#define PVP0_THC0_HFCNT_STAT        0xFFC1A480         /* PVP0 Current Frame counter */
+#define PVP0_THC1_HFCNT_STAT        0xFFC1A580         /* PVP0 Current Frame counter */
+#define PVP0_THC0_HCNT0_STAT        0xFFC1A484         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT0_STAT        0xFFC1A584         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT1_STAT        0xFFC1A488         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT1_STAT        0xFFC1A588         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT2_STAT        0xFFC1A48C         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT2_STAT        0xFFC1A58C         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT3_STAT        0xFFC1A490         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT3_STAT        0xFFC1A590         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT4_STAT        0xFFC1A494         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT4_STAT        0xFFC1A594         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT5_STAT        0xFFC1A498         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT5_STAT        0xFFC1A598         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT6_STAT        0xFFC1A49C         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT6_STAT        0xFFC1A59C         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT7_STAT        0xFFC1A4A0         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT7_STAT        0xFFC1A5A0         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT8_STAT        0xFFC1A4A4         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT8_STAT        0xFFC1A5A4         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT9_STAT        0xFFC1A4A8         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT9_STAT        0xFFC1A5A8         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT10_STAT       0xFFC1A4AC         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT10_STAT       0xFFC1A5AC         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT11_STAT       0xFFC1A4B0         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT11_STAT       0xFFC1A5B0         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT12_STAT       0xFFC1A4B4         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT12_STAT       0xFFC1A5B4         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT13_STAT       0xFFC1A4B8         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT13_STAT       0xFFC1A5B8         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT14_STAT       0xFFC1A4BC         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT14_STAT       0xFFC1A5BC         /* PVP0 Histogram counter value */
+#define PVP0_THC0_HCNT15_STAT       0xFFC1A4C0         /* PVP0 Histogram counter value */
+#define PVP0_THC1_HCNT15_STAT       0xFFC1A5C0         /* PVP0 Histogram counter value */
+#define PVP0_THC0_RREP_STAT         0xFFC1A4C4         /* PVP0 Number of RLE Reports */
+#define PVP0_THC1_RREP_STAT         0xFFC1A5C4         /* PVP0 Number of RLE Reports */
+#define PVP0_PMA_CFG                0xFFC1A600         /* PVP0 PMA Configuration Register */
+#define PWM0_CTL                    0xFFC1B000         /* PWM0 PWM Control Register */
+#define PWM0_CHANCFG                0xFFC1B004         /* PWM0 PWM Channel Config Register */
+#define PWM0_TRIPCFG                0xFFC1B008         /* PWM0 PWM Trip Config Register */
+#define PWM0_STAT                   0xFFC1B00C         /* PWM0 PWM Chop Config Register */
+#define PWM0_IMSK                   0xFFC1B010         /* PWM0 PWM Interrupt Mask Register */
+#define PWM0_ILAT                   0xFFC1B014         /* PWM0 PWM Interrupt Latch Register */
+#define PWM0_CHOPCFG                0xFFC1B018         /* PWM0 PWM Chop Configuration Register */
+#define PWM0_DT                     0xFFC1B01C         /* PWM0 PWM Dead Time Register */
+#define PWM0_SYNC_WID               0xFFC1B020         /* PWM0 Sync Pulse Width Register */
+#define PWM0_TM0                    0xFFC1B024         /* PWM0 Timer0 Period register */
+#define PWM0_TM1                    0xFFC1B028         /* PWM0 Timer1 Period register */
+#define PWM0_TM2                    0xFFC1B02C         /* PWM0 Timer2 Period register */
+#define PWM0_TM3                    0xFFC1B030         /* PWM0 Time3 Period register */
+#define PWM0_TM4                    0xFFC1B034         /* PWM0 Timer4 Period register */
+#define PWM0_DLYA                   0xFFC1B038         /* PWM0 Channel-A Delay register */
+#define PWM0_DLYB                   0xFFC1B03C         /* PWM0 Channel-B Delay register */
+#define PWM0_DLYC                   0xFFC1B040         /* PWM0 Channel-C Delay register */
+#define PWM0_DLYD                   0xFFC1B044         /* PWM0 Channel-D Delay register */
+#define PWM0_ACTL                   0xFFC1B048         /* PWM0 Channel-A control register */
+#define PWM0_AH0                    0xFFC1B04C         /* PWM0 Ch-AH Duty-0 register */
+#define PWM0_AH1                    0xFFC1B050         /* PWM0 Ch-AH Duty-1 register */
+#define PWM0_AH0_HP                 0xFFC1B054         /* PWM0 Ch-AH High precision Duty-0 register */
+#define PWM0_AH1_HP                 0xFFC1B058         /* PWM0 Ch-AH High precision Duty-1 register */
+#define PWM0_AL0                    0xFFC1B05C         /* PWM0 Ch-AL Duty-0 register */
+#define PWM0_AL1                    0xFFC1B060         /* PWM0 Ch-AL Duty-1 register */
+#define PWM0_BCTL                   0xFFC1B064         /* PWM0 Channel-B control register */
+#define PWM0_BH0                    0xFFC1B068         /* PWM0 Ch-BH Duty-0 register */
+#define PWM0_BH1                    0xFFC1B06C         /* PWM0 Ch-BH Duty-1 register */
+#define PWM0_BH0_HP                 0xFFC1B070         /* PWM0 Ch-BH High precision Duty-0 register */
+#define PWM0_BH1_HP                 0xFFC1B074         /* PWM0 Ch-BH High precision Duty-1 register */
+#define PWM0_BL0                    0xFFC1B078         /* PWM0 Ch-BL Duty-0 register */
+#define PWM0_BL1                    0xFFC1B07C         /* PWM0 Ch-BL Duty-1 register */
+#define PWM0_CCTL                   0xFFC1B080         /* PWM0 Channel-C control register */
+#define PWM0_CH0                    0xFFC1B084         /* PWM0 Ch-CH Duty-0 register */
+#define PWM0_CH1                    0xFFC1B088         /* PWM0 Ch-CH Duty-1 register */
+#define PWM0_CH0_HP                 0xFFC1B08C         /* PWM0 Ch-CH High precision Duty-0 register */
+#define PWM0_CH1_HP                 0xFFC1B090         /* PWM0 Ch-CH High precision Duty-1 register */
+#define PWM0_CL0                    0xFFC1B094         /* PWM0 Ch-CL Duty-0 register */
+#define PWM0_CL1                    0xFFC1B098         /* PWM0 Ch-CL Duty-1 register */
+#define PWM0_DCTL                   0xFFC1B09C         /* PWM0 Channel-D control register */
+#define PWM0_DH0                    0xFFC1B0A0         /* PWM0 Ch-DH Duty-0 register */
+#define PWM0_DH1                    0xFFC1B0A4         /* PWM0 Ch-DH Duty-1 register */
+#define PWM0_DH0_HP                 0xFFC1B0A8         /* PWM0 Ch-DH High precision Duty-0 register */
+#define PWM0_DH1_HP                 0xFFC1B0AC         /* PWM0 Ch-DH High precision Duty-1 register */
+#define PWM0_DL0                    0xFFC1B0B0         /* PWM0 Ch-DL Duty-0 register */
+#define PWM0_DL1                    0xFFC1B0B4         /* PWM0 Ch-DL Duty-1 register */
+#define PWM0_REVID                  0xFFC1B0FC         /* PWM0 PWM Revision ID Register */
+#define PWM1_CTL                    0xFFC1B400         /* PWM1 PWM Control Register */
+#define PWM1_CHANCFG                0xFFC1B404         /* PWM1 PWM Channel Config Register */
+#define PWM1_TRIPCFG                0xFFC1B408         /* PWM1 PWM Trip Config Register */
+#define PWM1_STAT                   0xFFC1B40C         /* PWM1 PWM Chop Config Register */
+#define PWM1_IMSK                   0xFFC1B410         /* PWM1 PWM Interrupt Mask Register */
+#define PWM1_ILAT                   0xFFC1B414         /* PWM1 PWM Interrupt Latch Register */
+#define PWM1_CHOPCFG                0xFFC1B418         /* PWM1 PWM Chop Configuration Register */
+#define PWM1_DT                     0xFFC1B41C         /* PWM1 PWM Dead Time Register */
+#define PWM1_SYNC_WID               0xFFC1B420         /* PWM1 Sync Pulse Width Register */
+#define PWM1_TM0                    0xFFC1B424         /* PWM1 Timer0 Period register */
+#define PWM1_TM1                    0xFFC1B428         /* PWM1 Timer1 Period register */
+#define PWM1_TM2                    0xFFC1B42C         /* PWM1 Timer2 Period register */
+#define PWM1_TM3                    0xFFC1B430         /* PWM1 Time3 Period register */
+#define PWM1_TM4                    0xFFC1B434         /* PWM1 Timer4 Period register */
+#define PWM1_DLYA                   0xFFC1B438         /* PWM1 Channel-A Delay register */
+#define PWM1_DLYB                   0xFFC1B43C         /* PWM1 Channel-B Delay register */
+#define PWM1_DLYC                   0xFFC1B440         /* PWM1 Channel-C Delay register */
+#define PWM1_DLYD                   0xFFC1B444         /* PWM1 Channel-D Delay register */
+#define PWM1_ACTL                   0xFFC1B448         /* PWM1 Channel-A control register */
+#define PWM1_AH0                    0xFFC1B44C         /* PWM1 Ch-AH Duty-0 register */
+#define PWM1_AH1                    0xFFC1B450         /* PWM1 Ch-AH Duty-1 register */
+#define PWM1_AH0_HP                 0xFFC1B454         /* PWM1 Ch-AH High precision Duty-0 register */
+#define PWM1_AH1_HP                 0xFFC1B458         /* PWM1 Ch-AH High precision Duty-1 register */
+#define PWM1_AL0                    0xFFC1B45C         /* PWM1 Ch-AL Duty-0 register */
+#define PWM1_AL1                    0xFFC1B460         /* PWM1 Ch-AL Duty-1 register */
+#define PWM1_BCTL                   0xFFC1B464         /* PWM1 Channel-B control register */
+#define PWM1_BH0                    0xFFC1B468         /* PWM1 Ch-BH Duty-0 register */
+#define PWM1_BH1                    0xFFC1B46C         /* PWM1 Ch-BH Duty-1 register */
+#define PWM1_BH0_HP                 0xFFC1B470         /* PWM1 Ch-BH High precision Duty-0 register */
+#define PWM1_BH1_HP                 0xFFC1B474         /* PWM1 Ch-BH High precision Duty-1 register */
+#define PWM1_BL0                    0xFFC1B478         /* PWM1 Ch-BL Duty-0 register */
+#define PWM1_BL1                    0xFFC1B47C         /* PWM1 Ch-BL Duty-1 register */
+#define PWM1_CCTL                   0xFFC1B480         /* PWM1 Channel-C control register */
+#define PWM1_CH0                    0xFFC1B484         /* PWM1 Ch-CH Duty-0 register */
+#define PWM1_CH1                    0xFFC1B488         /* PWM1 Ch-CH Duty-1 register */
+#define PWM1_CH0_HP                 0xFFC1B48C         /* PWM1 Ch-CH High precision Duty-0 register */
+#define PWM1_CH1_HP                 0xFFC1B490         /* PWM1 Ch-CH High precision Duty-1 register */
+#define PWM1_CL0                    0xFFC1B494         /* PWM1 Ch-CL Duty-0 register */
+#define PWM1_CL1                    0xFFC1B498         /* PWM1 Ch-CL Duty-1 register */
+#define PWM1_DCTL                   0xFFC1B49C         /* PWM1 Channel-D control register */
+#define PWM1_DH0                    0xFFC1B4A0         /* PWM1 Ch-DH Duty-0 register */
+#define PWM1_DH1                    0xFFC1B4A4         /* PWM1 Ch-DH Duty-1 register */
+#define PWM1_DH0_HP                 0xFFC1B4A8         /* PWM1 Ch-DH High precision Duty-0 register */
+#define PWM1_DH1_HP                 0xFFC1B4AC         /* PWM1 Ch-DH High precision Duty-1 register */
+#define PWM1_DL0                    0xFFC1B4B0         /* PWM1 Ch-DL Duty-0 register */
+#define PWM1_DL1                    0xFFC1B4B4         /* PWM1 Ch-DL Duty-1 register */
+#define PWM1_REVID                  0xFFC1B4FC         /* PWM1 PWM Revision ID Register */
+#define VID0_CONN                   0xFFC1D000         /* VID0 Video Subsystem Connect Register */
+#define SWU0_GCTL                   0xFFC1E000         /* SWU0 Global Control Register */
+#define SWU0_GSTAT                  0xFFC1E004         /* SWU0 Global Status Register */
+#define SWU0_CTL0                   0xFFC1E010         /* SWU0 Control Register n */
+#define SWU0_CTL1                   0xFFC1E030         /* SWU0 Control Register n */
+#define SWU0_CTL2                   0xFFC1E050         /* SWU0 Control Register n */
+#define SWU0_CTL3                   0xFFC1E070         /* SWU0 Control Register n */
+#define SWU0_LA0                    0xFFC1E014         /* SWU0 Lower Address Register n */
+#define SWU0_LA1                    0xFFC1E034         /* SWU0 Lower Address Register n */
+#define SWU0_LA2                    0xFFC1E054         /* SWU0 Lower Address Register n */
+#define SWU0_LA3                    0xFFC1E074         /* SWU0 Lower Address Register n */
+#define SWU0_UA0                    0xFFC1E018         /* SWU0 Upper Address Register n */
+#define SWU0_UA1                    0xFFC1E038         /* SWU0 Upper Address Register n */
+#define SWU0_UA2                    0xFFC1E058         /* SWU0 Upper Address Register n */
+#define SWU0_UA3                    0xFFC1E078         /* SWU0 Upper Address Register n */
+#define SWU0_ID0                    0xFFC1E01C         /* SWU0 ID Register n */
+#define SWU0_ID1                    0xFFC1E03C         /* SWU0 ID Register n */
+#define SWU0_ID2                    0xFFC1E05C         /* SWU0 ID Register n */
+#define SWU0_ID3                    0xFFC1E07C         /* SWU0 ID Register n */
+#define SWU0_CNT0                   0xFFC1E020         /* SWU0 Count Register n */
+#define SWU0_CNT1                   0xFFC1E040         /* SWU0 Count Register n */
+#define SWU0_CNT2                   0xFFC1E060         /* SWU0 Count Register n */
+#define SWU0_CNT3                   0xFFC1E080         /* SWU0 Count Register n */
+#define SWU0_TARG0                  0xFFC1E024         /* SWU0 Target Register n */
+#define SWU0_TARG1                  0xFFC1E044         /* SWU0 Target Register n */
+#define SWU0_TARG2                  0xFFC1E064         /* SWU0 Target Register n */
+#define SWU0_TARG3                  0xFFC1E084         /* SWU0 Target Register n */
+#define SWU0_HIST0                  0xFFC1E028         /* SWU0 Bandwidth History Register n */
+#define SWU0_HIST1                  0xFFC1E048         /* SWU0 Bandwidth History Register n */
+#define SWU0_HIST2                  0xFFC1E068         /* SWU0 Bandwidth History Register n */
+#define SWU0_HIST3                  0xFFC1E088         /* SWU0 Bandwidth History Register n */
+#define SWU0_CUR0                   0xFFC1E02C         /* SWU0 Current Register n */
+#define SWU0_CUR1                   0xFFC1E04C         /* SWU0 Current Register n */
+#define SWU0_CUR2                   0xFFC1E06C         /* SWU0 Current Register n */
+#define SWU0_CUR3                   0xFFC1E08C         /* SWU0 Current Register n */
+#define SWU1_GCTL                   0xFFCAB000         /* SWU1 Global Control Register */
+#define SWU1_GSTAT                  0xFFCAB004         /* SWU1 Global Status Register */
+#define SWU1_CTL0                   0xFFCAB010         /* SWU1 Control Register n */
+#define SWU1_CTL1                   0xFFCAB030         /* SWU1 Control Register n */
+#define SWU1_CTL2                   0xFFCAB050         /* SWU1 Control Register n */
+#define SWU1_CTL3                   0xFFCAB070         /* SWU1 Control Register n */
+#define SWU1_LA0                    0xFFCAB014         /* SWU1 Lower Address Register n */
+#define SWU1_LA1                    0xFFCAB034         /* SWU1 Lower Address Register n */
+#define SWU1_LA2                    0xFFCAB054         /* SWU1 Lower Address Register n */
+#define SWU1_LA3                    0xFFCAB074         /* SWU1 Lower Address Register n */
+#define SWU1_UA0                    0xFFCAB018         /* SWU1 Upper Address Register n */
+#define SWU1_UA1                    0xFFCAB038         /* SWU1 Upper Address Register n */
+#define SWU1_UA2                    0xFFCAB058         /* SWU1 Upper Address Register n */
+#define SWU1_UA3                    0xFFCAB078         /* SWU1 Upper Address Register n */
+#define SWU1_ID0                    0xFFCAB01C         /* SWU1 ID Register n */
+#define SWU1_ID1                    0xFFCAB03C         /* SWU1 ID Register n */
+#define SWU1_ID2                    0xFFCAB05C         /* SWU1 ID Register n */
+#define SWU1_ID3                    0xFFCAB07C         /* SWU1 ID Register n */
+#define SWU1_CNT0                   0xFFCAB020         /* SWU1 Count Register n */
+#define SWU1_CNT1                   0xFFCAB040         /* SWU1 Count Register n */
+#define SWU1_CNT2                   0xFFCAB060         /* SWU1 Count Register n */
+#define SWU1_CNT3                   0xFFCAB080         /* SWU1 Count Register n */
+#define SWU1_TARG0                  0xFFCAB024         /* SWU1 Target Register n */
+#define SWU1_TARG1                  0xFFCAB044         /* SWU1 Target Register n */
+#define SWU1_TARG2                  0xFFCAB064         /* SWU1 Target Register n */
+#define SWU1_TARG3                  0xFFCAB084         /* SWU1 Target Register n */
+#define SWU1_HIST0                  0xFFCAB028         /* SWU1 Bandwidth History Register n */
+#define SWU1_HIST1                  0xFFCAB048         /* SWU1 Bandwidth History Register n */
+#define SWU1_HIST2                  0xFFCAB068         /* SWU1 Bandwidth History Register n */
+#define SWU1_HIST3                  0xFFCAB088         /* SWU1 Bandwidth History Register n */
+#define SWU1_CUR0                   0xFFCAB02C         /* SWU1 Current Register n */
+#define SWU1_CUR1                   0xFFCAB04C         /* SWU1 Current Register n */
+#define SWU1_CUR2                   0xFFCAB06C         /* SWU1 Current Register n */
+#define SWU1_CUR3                   0xFFCAB08C         /* SWU1 Current Register n */
+#define SWU2_GCTL                   0xFFCAC000         /* SWU2 Global Control Register */
+#define SWU2_GSTAT                  0xFFCAC004         /* SWU2 Global Status Register */
+#define SWU2_CTL0                   0xFFCAC010         /* SWU2 Control Register n */
+#define SWU2_CTL1                   0xFFCAC030         /* SWU2 Control Register n */
+#define SWU2_CTL2                   0xFFCAC050         /* SWU2 Control Register n */
+#define SWU2_CTL3                   0xFFCAC070         /* SWU2 Control Register n */
+#define SWU2_LA0                    0xFFCAC014         /* SWU2 Lower Address Register n */
+#define SWU2_LA1                    0xFFCAC034         /* SWU2 Lower Address Register n */
+#define SWU2_LA2                    0xFFCAC054         /* SWU2 Lower Address Register n */
+#define SWU2_LA3                    0xFFCAC074         /* SWU2 Lower Address Register n */
+#define SWU2_UA0                    0xFFCAC018         /* SWU2 Upper Address Register n */
+#define SWU2_UA1                    0xFFCAC038         /* SWU2 Upper Address Register n */
+#define SWU2_UA2                    0xFFCAC058         /* SWU2 Upper Address Register n */
+#define SWU2_UA3                    0xFFCAC078         /* SWU2 Upper Address Register n */
+#define SWU2_ID0                    0xFFCAC01C         /* SWU2 ID Register n */
+#define SWU2_ID1                    0xFFCAC03C         /* SWU2 ID Register n */
+#define SWU2_ID2                    0xFFCAC05C         /* SWU2 ID Register n */
+#define SWU2_ID3                    0xFFCAC07C         /* SWU2 ID Register n */
+#define SWU2_CNT0                   0xFFCAC020         /* SWU2 Count Register n */
+#define SWU2_CNT1                   0xFFCAC040         /* SWU2 Count Register n */
+#define SWU2_CNT2                   0xFFCAC060         /* SWU2 Count Register n */
+#define SWU2_CNT3                   0xFFCAC080         /* SWU2 Count Register n */
+#define SWU2_TARG0                  0xFFCAC024         /* SWU2 Target Register n */
+#define SWU2_TARG1                  0xFFCAC044         /* SWU2 Target Register n */
+#define SWU2_TARG2                  0xFFCAC064         /* SWU2 Target Register n */
+#define SWU2_TARG3                  0xFFCAC084         /* SWU2 Target Register n */
+#define SWU2_HIST0                  0xFFCAC028         /* SWU2 Bandwidth History Register n */
+#define SWU2_HIST1                  0xFFCAC048         /* SWU2 Bandwidth History Register n */
+#define SWU2_HIST2                  0xFFCAC068         /* SWU2 Bandwidth History Register n */
+#define SWU2_HIST3                  0xFFCAC088         /* SWU2 Bandwidth History Register n */
+#define SWU2_CUR0                   0xFFCAC02C         /* SWU2 Current Register n */
+#define SWU2_CUR1                   0xFFCAC04C         /* SWU2 Current Register n */
+#define SWU2_CUR2                   0xFFCAC06C         /* SWU2 Current Register n */
+#define SWU2_CUR3                   0xFFCAC08C         /* SWU2 Current Register n */
+#define SWU3_GCTL                   0xFFCAD000         /* SWU3 Global Control Register */
+#define SWU3_GSTAT                  0xFFCAD004         /* SWU3 Global Status Register */
+#define SWU3_CTL0                   0xFFCAD010         /* SWU3 Control Register n */
+#define SWU3_CTL1                   0xFFCAD030         /* SWU3 Control Register n */
+#define SWU3_CTL2                   0xFFCAD050         /* SWU3 Control Register n */
+#define SWU3_CTL3                   0xFFCAD070         /* SWU3 Control Register n */
+#define SWU3_LA0                    0xFFCAD014         /* SWU3 Lower Address Register n */
+#define SWU3_LA1                    0xFFCAD034         /* SWU3 Lower Address Register n */
+#define SWU3_LA2                    0xFFCAD054         /* SWU3 Lower Address Register n */
+#define SWU3_LA3                    0xFFCAD074         /* SWU3 Lower Address Register n */
+#define SWU3_UA0                    0xFFCAD018         /* SWU3 Upper Address Register n */
+#define SWU3_UA1                    0xFFCAD038         /* SWU3 Upper Address Register n */
+#define SWU3_UA2                    0xFFCAD058         /* SWU3 Upper Address Register n */
+#define SWU3_UA3                    0xFFCAD078         /* SWU3 Upper Address Register n */
+#define SWU3_ID0                    0xFFCAD01C         /* SWU3 ID Register n */
+#define SWU3_ID1                    0xFFCAD03C         /* SWU3 ID Register n */
+#define SWU3_ID2                    0xFFCAD05C         /* SWU3 ID Register n */
+#define SWU3_ID3                    0xFFCAD07C         /* SWU3 ID Register n */
+#define SWU3_CNT0                   0xFFCAD020         /* SWU3 Count Register n */
+#define SWU3_CNT1                   0xFFCAD040         /* SWU3 Count Register n */
+#define SWU3_CNT2                   0xFFCAD060         /* SWU3 Count Register n */
+#define SWU3_CNT3                   0xFFCAD080         /* SWU3 Count Register n */
+#define SWU3_TARG0                  0xFFCAD024         /* SWU3 Target Register n */
+#define SWU3_TARG1                  0xFFCAD044         /* SWU3 Target Register n */
+#define SWU3_TARG2                  0xFFCAD064         /* SWU3 Target Register n */
+#define SWU3_TARG3                  0xFFCAD084         /* SWU3 Target Register n */
+#define SWU3_HIST0                  0xFFCAD028         /* SWU3 Bandwidth History Register n */
+#define SWU3_HIST1                  0xFFCAD048         /* SWU3 Bandwidth History Register n */
+#define SWU3_HIST2                  0xFFCAD068         /* SWU3 Bandwidth History Register n */
+#define SWU3_HIST3                  0xFFCAD088         /* SWU3 Bandwidth History Register n */
+#define SWU3_CUR0                   0xFFCAD02C         /* SWU3 Current Register n */
+#define SWU3_CUR1                   0xFFCAD04C         /* SWU3 Current Register n */
+#define SWU3_CUR2                   0xFFCAD06C         /* SWU3 Current Register n */
+#define SWU3_CUR3                   0xFFCAD08C         /* SWU3 Current Register n */
+#define SWU4_GCTL                   0xFFCAE000         /* SWU4 Global Control Register */
+#define SWU4_GSTAT                  0xFFCAE004         /* SWU4 Global Status Register */
+#define SWU4_CTL0                   0xFFCAE010         /* SWU4 Control Register n */
+#define SWU4_CTL1                   0xFFCAE030         /* SWU4 Control Register n */
+#define SWU4_CTL2                   0xFFCAE050         /* SWU4 Control Register n */
+#define SWU4_CTL3                   0xFFCAE070         /* SWU4 Control Register n */
+#define SWU4_LA0                    0xFFCAE014         /* SWU4 Lower Address Register n */
+#define SWU4_LA1                    0xFFCAE034         /* SWU4 Lower Address Register n */
+#define SWU4_LA2                    0xFFCAE054         /* SWU4 Lower Address Register n */
+#define SWU4_LA3                    0xFFCAE074         /* SWU4 Lower Address Register n */
+#define SWU4_UA0                    0xFFCAE018         /* SWU4 Upper Address Register n */
+#define SWU4_UA1                    0xFFCAE038         /* SWU4 Upper Address Register n */
+#define SWU4_UA2                    0xFFCAE058         /* SWU4 Upper Address Register n */
+#define SWU4_UA3                    0xFFCAE078         /* SWU4 Upper Address Register n */
+#define SWU4_ID0                    0xFFCAE01C         /* SWU4 ID Register n */
+#define SWU4_ID1                    0xFFCAE03C         /* SWU4 ID Register n */
+#define SWU4_ID2                    0xFFCAE05C         /* SWU4 ID Register n */
+#define SWU4_ID3                    0xFFCAE07C         /* SWU4 ID Register n */
+#define SWU4_CNT0                   0xFFCAE020         /* SWU4 Count Register n */
+#define SWU4_CNT1                   0xFFCAE040         /* SWU4 Count Register n */
+#define SWU4_CNT2                   0xFFCAE060         /* SWU4 Count Register n */
+#define SWU4_CNT3                   0xFFCAE080         /* SWU4 Count Register n */
+#define SWU4_TARG0                  0xFFCAE024         /* SWU4 Target Register n */
+#define SWU4_TARG1                  0xFFCAE044         /* SWU4 Target Register n */
+#define SWU4_TARG2                  0xFFCAE064         /* SWU4 Target Register n */
+#define SWU4_TARG3                  0xFFCAE084         /* SWU4 Target Register n */
+#define SWU4_HIST0                  0xFFCAE028         /* SWU4 Bandwidth History Register n */
+#define SWU4_HIST1                  0xFFCAE048         /* SWU4 Bandwidth History Register n */
+#define SWU4_HIST2                  0xFFCAE068         /* SWU4 Bandwidth History Register n */
+#define SWU4_HIST3                  0xFFCAE088         /* SWU4 Bandwidth History Register n */
+#define SWU4_CUR0                   0xFFCAE02C         /* SWU4 Current Register n */
+#define SWU4_CUR1                   0xFFCAE04C         /* SWU4 Current Register n */
+#define SWU4_CUR2                   0xFFCAE06C         /* SWU4 Current Register n */
+#define SWU4_CUR3                   0xFFCAE08C         /* SWU4 Current Register n */
+#define SWU5_GCTL                   0xFFCAF000         /* SWU5 Global Control Register */
+#define SWU5_GSTAT                  0xFFCAF004         /* SWU5 Global Status Register */
+#define SWU5_CTL0                   0xFFCAF010         /* SWU5 Control Register n */
+#define SWU5_CTL1                   0xFFCAF030         /* SWU5 Control Register n */
+#define SWU5_CTL2                   0xFFCAF050         /* SWU5 Control Register n */
+#define SWU5_CTL3                   0xFFCAF070         /* SWU5 Control Register n */
+#define SWU5_LA0                    0xFFCAF014         /* SWU5 Lower Address Register n */
+#define SWU5_LA1                    0xFFCAF034         /* SWU5 Lower Address Register n */
+#define SWU5_LA2                    0xFFCAF054         /* SWU5 Lower Address Register n */
+#define SWU5_LA3                    0xFFCAF074         /* SWU5 Lower Address Register n */
+#define SWU5_UA0                    0xFFCAF018         /* SWU5 Upper Address Register n */
+#define SWU5_UA1                    0xFFCAF038         /* SWU5 Upper Address Register n */
+#define SWU5_UA2                    0xFFCAF058         /* SWU5 Upper Address Register n */
+#define SWU5_UA3                    0xFFCAF078         /* SWU5 Upper Address Register n */
+#define SWU5_ID0                    0xFFCAF01C         /* SWU5 ID Register n */
+#define SWU5_ID1                    0xFFCAF03C         /* SWU5 ID Register n */
+#define SWU5_ID2                    0xFFCAF05C         /* SWU5 ID Register n */
+#define SWU5_ID3                    0xFFCAF07C         /* SWU5 ID Register n */
+#define SWU5_CNT0                   0xFFCAF020         /* SWU5 Count Register n */
+#define SWU5_CNT1                   0xFFCAF040         /* SWU5 Count Register n */
+#define SWU5_CNT2                   0xFFCAF060         /* SWU5 Count Register n */
+#define SWU5_CNT3                   0xFFCAF080         /* SWU5 Count Register n */
+#define SWU5_TARG0                  0xFFCAF024         /* SWU5 Target Register n */
+#define SWU5_TARG1                  0xFFCAF044         /* SWU5 Target Register n */
+#define SWU5_TARG2                  0xFFCAF064         /* SWU5 Target Register n */
+#define SWU5_TARG3                  0xFFCAF084         /* SWU5 Target Register n */
+#define SWU5_HIST0                  0xFFCAF028         /* SWU5 Bandwidth History Register n */
+#define SWU5_HIST1                  0xFFCAF048         /* SWU5 Bandwidth History Register n */
+#define SWU5_HIST2                  0xFFCAF068         /* SWU5 Bandwidth History Register n */
+#define SWU5_HIST3                  0xFFCAF088         /* SWU5 Bandwidth History Register n */
+#define SWU5_CUR0                   0xFFCAF02C         /* SWU5 Current Register n */
+#define SWU5_CUR1                   0xFFCAF04C         /* SWU5 Current Register n */
+#define SWU5_CUR2                   0xFFCAF06C         /* SWU5 Current Register n */
+#define SWU5_CUR3                   0xFFCAF08C         /* SWU5 Current Register n */
+#define SWU6_GCTL                   0xFFC82000         /* SWU6 Global Control Register */
+#define SWU6_GSTAT                  0xFFC82004         /* SWU6 Global Status Register */
+#define SWU6_CTL0                   0xFFC82010         /* SWU6 Control Register n */
+#define SWU6_CTL1                   0xFFC82030         /* SWU6 Control Register n */
+#define SWU6_CTL2                   0xFFC82050         /* SWU6 Control Register n */
+#define SWU6_CTL3                   0xFFC82070         /* SWU6 Control Register n */
+#define SWU6_LA0                    0xFFC82014         /* SWU6 Lower Address Register n */
+#define SWU6_LA1                    0xFFC82034         /* SWU6 Lower Address Register n */
+#define SWU6_LA2                    0xFFC82054         /* SWU6 Lower Address Register n */
+#define SWU6_LA3                    0xFFC82074         /* SWU6 Lower Address Register n */
+#define SWU6_UA0                    0xFFC82018         /* SWU6 Upper Address Register n */
+#define SWU6_UA1                    0xFFC82038         /* SWU6 Upper Address Register n */
+#define SWU6_UA2                    0xFFC82058         /* SWU6 Upper Address Register n */
+#define SWU6_UA3                    0xFFC82078         /* SWU6 Upper Address Register n */
+#define SWU6_ID0                    0xFFC8201C         /* SWU6 ID Register n */
+#define SWU6_ID1                    0xFFC8203C         /* SWU6 ID Register n */
+#define SWU6_ID2                    0xFFC8205C         /* SWU6 ID Register n */
+#define SWU6_ID3                    0xFFC8207C         /* SWU6 ID Register n */
+#define SWU6_CNT0                   0xFFC82020         /* SWU6 Count Register n */
+#define SWU6_CNT1                   0xFFC82040         /* SWU6 Count Register n */
+#define SWU6_CNT2                   0xFFC82060         /* SWU6 Count Register n */
+#define SWU6_CNT3                   0xFFC82080         /* SWU6 Count Register n */
+#define SWU6_TARG0                  0xFFC82024         /* SWU6 Target Register n */
+#define SWU6_TARG1                  0xFFC82044         /* SWU6 Target Register n */
+#define SWU6_TARG2                  0xFFC82064         /* SWU6 Target Register n */
+#define SWU6_TARG3                  0xFFC82084         /* SWU6 Target Register n */
+#define SWU6_HIST0                  0xFFC82028         /* SWU6 Bandwidth History Register n */
+#define SWU6_HIST1                  0xFFC82048         /* SWU6 Bandwidth History Register n */
+#define SWU6_HIST2                  0xFFC82068         /* SWU6 Bandwidth History Register n */
+#define SWU6_HIST3                  0xFFC82088         /* SWU6 Bandwidth History Register n */
+#define SWU6_CUR0                   0xFFC8202C         /* SWU6 Current Register n */
+#define SWU6_CUR1                   0xFFC8204C         /* SWU6 Current Register n */
+#define SWU6_CUR2                   0xFFC8206C         /* SWU6 Current Register n */
+#define SWU6_CUR3                   0xFFC8208C         /* SWU6 Current Register n */
+#define SDU0_IDCODE                 0xFFC1F020         /* SDU0 ID Code Register */
+#define SDU0_CTL                    0xFFC1F050         /* SDU0 Control Register */
+#define SDU0_STAT                   0xFFC1F054         /* SDU0 Status Register */
+#define SDU0_MACCTL                 0xFFC1F058         /* SDU0 Memory Access Control Register */
+#define SDU0_MACADDR                0xFFC1F05C         /* SDU0 Memory Access Address Register */
+#define SDU0_MACDATA                0xFFC1F060         /* SDU0 Memory Access Data Register */
+#define SDU0_DMARD                  0xFFC1F064         /* SDU0 DMA Read Data Register */
+#define SDU0_DMAWD                  0xFFC1F068         /* SDU0 DMA Write Data Register */
+#define SDU0_MSG                    0xFFC1F080         /* SDU0 Message Register */
+#define SDU0_MSG_SET                0xFFC1F084         /* SDU0 Message Set Register */
+#define SDU0_MSG_CLR                0xFFC1F088         /* SDU0 Message Clear Register */
+#define SDU0_GHLT                   0xFFC1F08C         /* SDU0 Group Halt Register */
+#define EMAC0_MACCFG                0xFFC20000         /* EMAC0 MAC Configuration Register */
+#define EMAC0_MACFRMFILT            0xFFC20004         /* EMAC0 Filter Register for filtering Received Frames */
+#define EMAC0_HASHTBL_HI            0xFFC20008         /* EMAC0 Contains the Upper 32 bits of the hash table */
+#define EMAC0_HASHTBL_LO            0xFFC2000C         /* EMAC0 Contains the lower 32 bits of the hash table */
+#define EMAC0_GMII_ADDR             0xFFC20010         /* EMAC0 Management Address Register */
+#define EMAC0_GMII_DATA             0xFFC20014         /* EMAC0 Management Data Register */
+#define EMAC0_FLOWCTL               0xFFC20018         /* EMAC0 MAC FLow Control Register */
+#define EMAC0_VLANTAG               0xFFC2001C         /* EMAC0 VLAN Tag Register */
+#define EMAC0_VER                   0xFFC20020         /* EMAC0 EMAC Version Register */
+#define EMAC0_DBG                   0xFFC20024         /* EMAC0 EMAC Debug Register */
+#define EMAC0_RMTWKUP               0xFFC20028         /* EMAC0 Remote wake up frame register */
+#define EMAC0_PMT_CTLSTAT           0xFFC2002C         /* EMAC0 PMT Control and Status Register */
+#define EMAC0_ISTAT                 0xFFC20038         /* EMAC0 EMAC Interrupt Status Register */
+#define EMAC0_IMSK                  0xFFC2003C         /* EMAC0 EMAC Interrupt Mask Register */
+#define EMAC0_ADDR0_HI              0xFFC20040         /* EMAC0 EMAC Address0 High Register */
+#define EMAC0_ADDR0_LO              0xFFC20044         /* EMAC0 EMAC Address0 Low Register */
+#define EMAC0_MMC_CTL               0xFFC20100         /* EMAC0 MMC Control Register */
+#define EMAC0_MMC_RXINT             0xFFC20104         /* EMAC0 MMC RX Interrupt Register */
+#define EMAC0_MMC_TXINT             0xFFC20108         /* EMAC0 MMC TX Interrupt Register */
+#define EMAC0_MMC_RXIMSK            0xFFC2010C         /* EMAC0 MMC RX Interrupt Mask Register */
+#define EMAC0_MMC_TXIMSK            0xFFC20110         /* EMAC0 MMC TX Interrupt Mask Register */
+#define EMAC0_TXOCTCNT_GB           0xFFC20114         /* EMAC0 Num bytes transmitted exclusive of preamble */
+#define EMAC0_TXFRMCNT_GB           0xFFC20118         /* EMAC0 Num frames transmitted exclusive of retired */
+#define EMAC0_TXBCASTFRM_G          0xFFC2011C         /* EMAC0 Number of good broadcast frames transmitted. */
+#define EMAC0_TXMCASTFRM_G          0xFFC20120         /* EMAC0 Number of good multicast frames transmitted. */
+#define EMAC0_TX64_GB               0xFFC20124         /* EMAC0 Number of 64 byte length frames */
+#define EMAC0_TX65TO127_GB          0xFFC20128         /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
+#define EMAC0_TX128TO255_GB         0xFFC2012C         /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
+#define EMAC0_TX256TO511_GB         0xFFC20130         /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
+#define EMAC0_TX512TO1023_GB        0xFFC20134         /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
+#define EMAC0_TX1024TOMAX_GB        0xFFC20138         /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
+#define EMAC0_TXUCASTFRM_GB         0xFFC2013C         /* EMAC0 Number of good and bad unicast frames transmitted */
+#define EMAC0_TXMCASTFRM_GB         0xFFC20140         /* EMAC0 Number of good and bad multicast frames transmitted */
+#define EMAC0_TXBCASTFRM_GB         0xFFC20144         /* EMAC0 Number of good and bad broadcast frames transmitted */
+#define EMAC0_TXUNDR_ERR            0xFFC20148         /* EMAC0 Number of frames aborted due to frame underflow error */
+#define EMAC0_TXSNGCOL_G            0xFFC2014C         /* EMAC0 Number of transmitted frames after single collision */
+#define EMAC0_TXMULTCOL_G           0xFFC20150         /* EMAC0 Number of transmitted frames with more than one collision */
+#define EMAC0_TXDEFERRED            0xFFC20154         /* EMAC0 Number of transmitted frames after deferral */
+#define EMAC0_TXLATECOL             0xFFC20158         /* EMAC0 Number of frames aborted due to late collision error */
+#define EMAC0_TXEXCESSCOL           0xFFC2015C         /* EMAC0 Number of aborted frames due to excessive collisions */
+#define EMAC0_TXCARR_ERR            0xFFC20160         /* EMAC0 Number of aborted frames due to carrier sense error */
+#define EMAC0_TXOCTCNT_G            0xFFC20164         /* EMAC0 Number of bytes transmitted in good frames only */
+#define EMAC0_TXFRMCNT_G            0xFFC20168         /* EMAC0 Number of good frames transmitted. */
+#define EMAC0_TXEXCESSDEF           0xFFC2016C         /* EMAC0 Number of frames aborted due to excessive deferral */
+#define EMAC0_TXPAUSEFRM            0xFFC20170         /* EMAC0 Number of good PAUSE frames transmitted. */
+#define EMAC0_TXVLANFRM_G           0xFFC20174         /* EMAC0 Number of VLAN frames transmitted */
+#define EMAC0_RXFRMCNT_GB           0xFFC20180         /* EMAC0 Number of good and bad frames received. */
+#define EMAC0_RXOCTCNT_GB           0xFFC20184         /* EMAC0 Number of bytes received in good and bad frames */
+#define EMAC0_RXOCTCNT_G            0xFFC20188         /* EMAC0 Number of bytes received only in good frames */
+#define EMAC0_RXBCASTFRM_G          0xFFC2018C         /* EMAC0 Number of good broadcast frames received. */
+#define EMAC0_RXMCASTFRM_G          0xFFC20190         /* EMAC0 Number of good multicast frames received */
+#define EMAC0_RXCRC_ERR             0xFFC20194         /* EMAC0 Number of frames received with CRC error */
+#define EMAC0_RXALIGN_ERR           0xFFC20198         /* EMAC0 Number of frames with alignment error */
+#define EMAC0_RXRUNT_ERR            0xFFC2019C         /* EMAC0 Number of frames received with runt error. */
+#define EMAC0_RXJAB_ERR             0xFFC201A0         /* EMAC0 Number of frames received with length greater than 1518 */
+#define EMAC0_RXUSIZE_G             0xFFC201A4         /* EMAC0 Number of frames received with length 64 */
+#define EMAC0_RXOSIZE_G             0xFFC201A8         /* EMAC0 Number of frames received with length greater than maxium */
+#define EMAC0_RX64_GB               0xFFC201AC         /* EMAC0 Number of good and bad frames of lengh 64 bytes */
+#define EMAC0_RX65TO127_GB          0xFFC201B0         /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
+#define EMAC0_RX128TO255_GB         0xFFC201B4         /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
+#define EMAC0_RX256TO511_GB         0xFFC201B8         /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
+#define EMAC0_RX512TO1023_GB        0xFFC201BC         /* EMAC0 Number of good and bad frames received between 512-1023 */
+#define EMAC0_RX1024TOMAX_GB        0xFFC201C0         /* EMAC0 Number of frames received between 1024 and maxsize */
+#define EMAC0_RXUCASTFRM_G          0xFFC201C4         /* EMAC0 Number of good unicast frames received. */
+#define EMAC0_RXLEN_ERR             0xFFC201C8         /* EMAC0 Number of frames received with length error */
+#define EMAC0_RXOORTYPE             0xFFC201CC         /* EMAC0 Number of frames with length not equal to valid frame size */
+#define EMAC0_RXPAUSEFRM            0xFFC201D0         /* EMAC0 Number of good and valid PAUSE frames received. */
+#define EMAC0_RXFIFO_OVF            0xFFC201D4         /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
+#define EMAC0_RXVLANFRM_GB          0xFFC201D8         /* EMAC0 Number of good and bad VLAN frames received. */
+#define EMAC0_RXWDOG_ERR            0xFFC201DC         /* EMAC0 Frames received with error due to watchdog timeout */
+#define EMAC0_IPC_RXIMSK            0xFFC20200         /* EMAC0 MMC IPC RX Interrupt Mask Register */
+#define EMAC0_IPC_RXINT             0xFFC20208         /* EMAC0 MMC IPC RX Interrupt Register */
+#define EMAC0_RXIPV4_GD_FRM         0xFFC20210         /* EMAC0 Number of good IPv4 datagrams */
+#define EMAC0_RXIPV4_HDR_ERR_FRM    0xFFC20214         /* EMAC0 Number of IPv4 datagrams with header errors */
+#define EMAC0_RXIPV4_NOPAY_FRM      0xFFC20218         /* EMAC0 Number of IPv4 datagrams without checksum */
+#define EMAC0_RXIPV4_FRAG_FRM       0xFFC2021C         /* EMAC0 Number of good IPv4 datagrams with fragmentation */
+#define EMAC0_RXIPV4_UDSBL_FRM      0xFFC20220         /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
+#define EMAC0_RXIPV6_GD_FRM         0xFFC20224         /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
+#define EMAC0_RXIPV6_HDR_ERR_FRM    0xFFC20228         /* EMAC0 Number of IPv6 datagrams with header errors */
+#define EMAC0_RXIPV6_NOPAY_FRM      0xFFC2022C         /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
+#define EMAC0_RXUDP_GD_FRM          0xFFC20230         /* EMAC0 Number of good IP datagrames with good UDP payload */
+#define EMAC0_RXUDP_ERR_FRM         0xFFC20234         /* EMAC0 Number of good IP datagrams with UDP checksum errors */
+#define EMAC0_RXTCP_GD_FRM          0xFFC20238         /* EMAC0 Number of good IP datagrams with a good TCP payload */
+#define EMAC0_RXTCP_ERR_FRM         0xFFC2023C         /* EMAC0 Number of good IP datagrams with TCP checksum errors */
+#define EMAC0_RXICMP_GD_FRM         0xFFC20240         /* EMAC0 Number of good IP datagrams with a good ICMP payload */
+#define EMAC0_RXICMP_ERR_FRM        0xFFC20244         /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
+#define EMAC0_RXIPV4_GD_OCT         0xFFC20250         /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
+#define EMAC0_RXIPV4_HDR_ERR_OCT    0xFFC20254         /* EMAC0 Bytes received in IPv4 datagrams with header errors */
+#define EMAC0_RXIPV4_NOPAY_OCT      0xFFC20258         /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
+#define EMAC0_RXIPV4_FRAG_OCT       0xFFC2025C         /* EMAC0 Bytes received in fragmented IPv4 datagrams */
+#define EMAC0_RXIPV4_UDSBL_OCT      0xFFC20260         /* EMAC0 Bytes received in UDP segment with checksum disabled */
+#define EMAC0_RXIPV6_GD_OCT         0xFFC20264         /* EMAC0 Bytes received in good IPv6  including tcp,udp or icmp load */
+#define EMAC0_RXIPV6_HDR_ERR_OCT    0xFFC20268         /* EMAC0 Number of bytes received in IPv6 with header errors */
+#define EMAC0_RXIPV6_NOPAY_OCT      0xFFC2026C         /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
+#define EMAC0_RXUDP_GD_OCT          0xFFC20270         /* EMAC0 Number of bytes received in good UDP segments */
+#define EMAC0_RXUDP_ERR_OCT         0xFFC20274         /* EMAC0 Number of bytes received in UDP segment with checksum err */
+#define EMAC0_RXTCP_GD_OCT          0xFFC20278         /* EMAC0 Number of bytes received in a good TCP segment */
+#define EMAC0_RXTCP_ERR_OCT         0xFFC2027C         /* EMAC0 Number of bytes received in TCP segment with checksum err */
+#define EMAC0_RXICMP_GD_OCT         0xFFC20280         /* EMAC0 Number of bytes received in a good ICMP segment */
+#define EMAC0_RXICMP_ERR_OCT        0xFFC20284         /* EMAC0 Bytes received in an ICMP segment with checksum errors */
+#define EMAC0_TM_CTL                0xFFC20700         /* EMAC0 EMAC Time Stamp Control Register */
+#define EMAC0_TM_SUBSEC             0xFFC20704         /* EMAC0 EMAC Time Stamp Sub Second Increment */
+#define EMAC0_TM_SEC                0xFFC20708         /* EMAC0 EMAC Time Stamp Second Register */
+#define EMAC0_TM_NSEC               0xFFC2070C         /* EMAC0 EMAC Time Stamp Nano Second Register */
+#define EMAC0_TM_SECUPDT            0xFFC20710         /* EMAC0 EMAC Time Stamp Seconds Update */
+#define EMAC0_TM_NSECUPDT           0xFFC20714         /* EMAC0 EMAC Time Stamp Nano Seconds Update */
+#define EMAC0_TM_ADDEND             0xFFC20718         /* EMAC0 EMAC Time Stamp Addend Register */
+#define EMAC0_TM_TGTM               0xFFC2071C         /* EMAC0 EMAC Time Stamp Target Time Sec. */
+#define EMAC0_TM_NTGTM              0xFFC20720         /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
+#define EMAC0_TM_HISEC              0xFFC20724         /* EMAC0 EMAC Time Stamp High Second Register */
+#define EMAC0_TM_STMPSTAT           0xFFC20728         /* EMAC0 EMAC Time Stamp Status Register */
+#define EMAC0_TM_PPSCTL             0xFFC2072C         /* EMAC0 EMAC PPS Control Register */
+#define EMAC0_TM_AUXSTMP_NSEC       0xFFC20730         /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
+#define EMAC0_TM_AUXSTMP_SEC        0xFFC20734         /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
+#define EMAC0_DMA_BUSMODE           0xFFC21000         /* EMAC0 Bus Operating Modes for EMAC DMA */
+#define EMAC0_DMA_TXPOLL            0xFFC21004         /* EMAC0 TX DMA Poll demand register */
+#define EMAC0_DMA_RXPOLL            0xFFC21008         /* EMAC0 RX DMA Poll demand register */
+#define EMAC0_DMA_RXDSC_ADDR        0xFFC2100C         /* EMAC0 RX Descriptor List Address */
+#define EMAC0_DMA_TXDSC_ADDR        0xFFC21010         /* EMAC0 TX Descriptor List Address */
+#define EMAC0_DMA_STAT              0xFFC21014         /* EMAC0 DMA Status Register */
+#define EMAC0_DMA_OPMODE            0xFFC21018         /* EMAC0 DMA Operation Mode Register */
+#define EMAC0_DMA_IEN               0xFFC2101C         /* EMAC0 DMA Interrupt Enable Register */
+#define EMAC0_DMA_MISS_FRM          0xFFC21020         /* EMAC0 DMA missed frame and buffer overflow counter */
+#define EMAC0_DMA_RXIWDOG           0xFFC21024         /* EMAC0 DMA RX Interrupt Watch Dog timer */
+#define EMAC0_DMA_BMMODE            0xFFC21028         /* EMAC0 AXI Bus Mode Register */
+#define EMAC0_DMA_BMSTAT            0xFFC2102C         /* EMAC0 AXI Status Register */
+#define EMAC0_DMA_TXDSC_CUR         0xFFC21048         /* EMAC0 TX current descriptor register */
+#define EMAC0_DMA_RXDSC_CUR         0xFFC2104C         /* EMAC0 RX current descriptor register */
+#define EMAC0_DMA_TXBUF_CUR         0xFFC21050         /* EMAC0 TX current buffer pointer register */
+#define EMAC0_DMA_RXBUF_CUR         0xFFC21054         /* EMAC0 RX current buffer pointer register */
+#define EMAC0_HWFEAT                0xFFC21058         /* EMAC0 Hardware Feature Register */
+#define EMAC1_MACCFG                0xFFC22000         /* EMAC1 MAC Configuration Register */
+#define EMAC1_MACFRMFILT            0xFFC22004         /* EMAC1 Filter Register for filtering Received Frames */
+#define EMAC1_HASHTBL_HI            0xFFC22008         /* EMAC1 Contains the Upper 32 bits of the hash table */
+#define EMAC1_HASHTBL_LO            0xFFC2200C         /* EMAC1 Contains the lower 32 bits of the hash table */
+#define EMAC1_GMII_ADDR             0xFFC22010         /* EMAC1 Management Address Register */
+#define EMAC1_GMII_DATA             0xFFC22014         /* EMAC1 Management Data Register */
+#define EMAC1_FLOWCTL               0xFFC22018         /* EMAC1 MAC FLow Control Register */
+#define EMAC1_VLANTAG               0xFFC2201C         /* EMAC1 VLAN Tag Register */
+#define EMAC1_VER                   0xFFC22020         /* EMAC1 EMAC Version Register */
+#define EMAC1_DBG                   0xFFC22024         /* EMAC1 EMAC Debug Register */
+#define EMAC1_RMTWKUP               0xFFC22028         /* EMAC1 Remote wake up frame register */
+#define EMAC1_PMT_CTLSTAT           0xFFC2202C         /* EMAC1 PMT Control and Status Register */
+#define EMAC1_ISTAT                 0xFFC22038         /* EMAC1 EMAC Interrupt Status Register */
+#define EMAC1_IMSK                  0xFFC2203C         /* EMAC1 EMAC Interrupt Mask Register */
+#define EMAC1_ADDR0_HI              0xFFC22040         /* EMAC1 EMAC Address0 High Register */
+#define EMAC1_ADDR0_LO              0xFFC22044         /* EMAC1 EMAC Address0 Low Register */
+#define EMAC1_MMC_CTL               0xFFC22100         /* EMAC1 MMC Control Register */
+#define EMAC1_MMC_RXINT             0xFFC22104         /* EMAC1 MMC RX Interrupt Register */
+#define EMAC1_MMC_TXINT             0xFFC22108         /* EMAC1 MMC TX Interrupt Register */
+#define EMAC1_MMC_RXIMSK            0xFFC2210C         /* EMAC1 MMC RX Interrupt Mask Register */
+#define EMAC1_MMC_TXIMSK            0xFFC22110         /* EMAC1 MMC TX Interrupt Mask Register */
+#define EMAC1_TXOCTCNT_GB           0xFFC22114         /* EMAC1 Num bytes transmitted exclusive of preamble */
+#define EMAC1_TXFRMCNT_GB           0xFFC22118         /* EMAC1 Num frames transmitted exclusive of retired */
+#define EMAC1_TXBCASTFRM_G          0xFFC2211C         /* EMAC1 Number of good broadcast frames transmitted. */
+#define EMAC1_TXMCASTFRM_G          0xFFC22120         /* EMAC1 Number of good multicast frames transmitted. */
+#define EMAC1_TX64_GB               0xFFC22124         /* EMAC1 Number of 64 byte length frames */
+#define EMAC1_TX65TO127_GB          0xFFC22128         /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
+#define EMAC1_TX128TO255_GB         0xFFC2212C         /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
+#define EMAC1_TX256TO511_GB         0xFFC22130         /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
+#define EMAC1_TX512TO1023_GB        0xFFC22134         /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
+#define EMAC1_TX1024TOMAX_GB        0xFFC22138         /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
+#define EMAC1_TXUCASTFRM_GB         0xFFC2213C         /* EMAC1 Number of good and bad unicast frames transmitted */
+#define EMAC1_TXMCASTFRM_GB         0xFFC22140         /* EMAC1 Number of good and bad multicast frames transmitted */
+#define EMAC1_TXBCASTFRM_GB         0xFFC22144         /* EMAC1 Number of good and bad broadcast frames transmitted */
+#define EMAC1_TXUNDR_ERR            0xFFC22148         /* EMAC1 Number of frames aborted due to frame underflow error */
+#define EMAC1_TXSNGCOL_G            0xFFC2214C         /* EMAC1 Number of transmitted frames after single collision */
+#define EMAC1_TXMULTCOL_G           0xFFC22150         /* EMAC1 Number of transmitted frames with more than one collision */
+#define EMAC1_TXDEFERRED            0xFFC22154         /* EMAC1 Number of transmitted frames after deferral */
+#define EMAC1_TXLATECOL             0xFFC22158         /* EMAC1 Number of frames aborted due to late collision error */
+#define EMAC1_TXEXCESSCOL           0xFFC2215C         /* EMAC1 Number of aborted frames due to excessive collisions */
+#define EMAC1_TXCARR_ERR            0xFFC22160         /* EMAC1 Number of aborted frames due to carrier sense error */
+#define EMAC1_TXOCTCNT_G            0xFFC22164         /* EMAC1 Number of bytes transmitted in good frames only */
+#define EMAC1_TXFRMCNT_G            0xFFC22168         /* EMAC1 Number of good frames transmitted. */
+#define EMAC1_TXEXCESSDEF           0xFFC2216C         /* EMAC1 Number of frames aborted due to excessive deferral */
+#define EMAC1_TXPAUSEFRM            0xFFC22170         /* EMAC1 Number of good PAUSE frames transmitted. */
+#define EMAC1_TXVLANFRM_G           0xFFC22174         /* EMAC1 Number of VLAN frames transmitted */
+#define EMAC1_RXFRMCNT_GB           0xFFC22180         /* EMAC1 Number of good and bad frames received. */
+#define EMAC1_RXOCTCNT_GB           0xFFC22184         /* EMAC1 Number of bytes received in good and bad frames */
+#define EMAC1_RXOCTCNT_G            0xFFC22188         /* EMAC1 Number of bytes received only in good frames */
+#define EMAC1_RXBCASTFRM_G          0xFFC2218C         /* EMAC1 Number of good broadcast frames received. */
+#define EMAC1_RXMCASTFRM_G          0xFFC22190         /* EMAC1 Number of good multicast frames received */
+#define EMAC1_RXCRC_ERR             0xFFC22194         /* EMAC1 Number of frames received with CRC error */
+#define EMAC1_RXALIGN_ERR           0xFFC22198         /* EMAC1 Number of frames with alignment error */
+#define EMAC1_RXRUNT_ERR            0xFFC2219C         /* EMAC1 Number of frames received with runt error. */
+#define EMAC1_RXJAB_ERR             0xFFC221A0         /* EMAC1 Number of frames received with length greater than 1518 */
+#define EMAC1_RXUSIZE_G             0xFFC221A4         /* EMAC1 Number of frames received with length 64 */
+#define EMAC1_RXOSIZE_G             0xFFC221A8         /* EMAC1 Number of frames received with length greater than maxium */
+#define EMAC1_RX64_GB               0xFFC221AC         /* EMAC1 Number of good and bad frames of lengh 64 bytes */
+#define EMAC1_RX65TO127_GB          0xFFC221B0         /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
+#define EMAC1_RX128TO255_GB         0xFFC221B4         /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
+#define EMAC1_RX256TO511_GB         0xFFC221B8         /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
+#define EMAC1_RX512TO1023_GB        0xFFC221BC         /* EMAC1 Number of good and bad frames received between 512-1023 */
+#define EMAC1_RX1024TOMAX_GB        0xFFC221C0         /* EMAC1 Number of frames received between 1024 and maxsize */
+#define EMAC1_RXUCASTFRM_G          0xFFC221C4         /* EMAC1 Number of good unicast frames received. */
+#define EMAC1_RXLEN_ERR             0xFFC221C8         /* EMAC1 Number of frames received with length error */
+#define EMAC1_RXOORTYPE             0xFFC221CC         /* EMAC1 Number of frames with length not equal to valid frame size */
+#define EMAC1_RXPAUSEFRM            0xFFC221D0         /* EMAC1 Number of good and valid PAUSE frames received. */
+#define EMAC1_RXFIFO_OVF            0xFFC221D4         /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
+#define EMAC1_RXVLANFRM_GB          0xFFC221D8         /* EMAC1 Number of good and bad VLAN frames received. */
+#define EMAC1_RXWDOG_ERR            0xFFC221DC         /* EMAC1 Frames received with error due to watchdog timeout */
+#define EMAC1_IPC_RXIMSK            0xFFC22200         /* EMAC1 MMC IPC RX Interrupt Mask Register */
+#define EMAC1_IPC_RXINT             0xFFC22208         /* EMAC1 MMC IPC RX Interrupt Register */
+#define EMAC1_RXIPV4_GD_FRM         0xFFC22210         /* EMAC1 Number of good IPv4 datagrams */
+#define EMAC1_RXIPV4_HDR_ERR_FRM    0xFFC22214         /* EMAC1 Number of IPv4 datagrams with header errors */
+#define EMAC1_RXIPV4_NOPAY_FRM      0xFFC22218         /* EMAC1 Number of IPv4 datagrams without checksum */
+#define EMAC1_RXIPV4_FRAG_FRM       0xFFC2221C         /* EMAC1 Number of good IPv4 datagrams with fragmentation */
+#define EMAC1_RXIPV4_UDSBL_FRM      0xFFC22220         /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
+#define EMAC1_RXIPV6_GD_FRM         0xFFC22224         /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
+#define EMAC1_RXIPV6_HDR_ERR_FRM    0xFFC22228         /* EMAC1 Number of IPv6 datagrams with header errors */
+#define EMAC1_RXIPV6_NOPAY_FRM      0xFFC2222C         /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
+#define EMAC1_RXUDP_GD_FRM          0xFFC22230         /* EMAC1 Number of good IP datagrames with good UDP payload */
+#define EMAC1_RXUDP_ERR_FRM         0xFFC22234         /* EMAC1 Number of good IP datagrams with UDP checksum errors */
+#define EMAC1_RXTCP_GD_FRM          0xFFC22238         /* EMAC1 Number of good IP datagrams with a good TCP payload */
+#define EMAC1_RXTCP_ERR_FRM         0xFFC2223C         /* EMAC1 Number of good IP datagrams with TCP checksum errors */
+#define EMAC1_RXICMP_GD_FRM         0xFFC22240         /* EMAC1 Number of good IP datagrams with a good ICMP payload */
+#define EMAC1_RXICMP_ERR_FRM        0xFFC22244         /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
+#define EMAC1_RXIPV4_GD_OCT         0xFFC22250         /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
+#define EMAC1_RXIPV4_HDR_ERR_OCT    0xFFC22254         /* EMAC1 Bytes received in IPv4 datagrams with header errors */
+#define EMAC1_RXIPV4_NOPAY_OCT      0xFFC22258         /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
+#define EMAC1_RXIPV4_FRAG_OCT       0xFFC2225C         /* EMAC1 Bytes received in fragmented IPv4 datagrams */
+#define EMAC1_RXIPV4_UDSBL_OCT      0xFFC22260         /* EMAC1 Bytes received in UDP segment with checksum disabled */
+#define EMAC1_RXIPV6_GD_OCT         0xFFC22264         /* EMAC1 Bytes received in good IPv6  including tcp,udp or icmp load */
+#define EMAC1_RXIPV6_HDR_ERR_OCT    0xFFC22268         /* EMAC1 Number of bytes received in IPv6 with header errors */
+#define EMAC1_RXIPV6_NOPAY_OCT      0xFFC2226C         /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
+#define EMAC1_RXUDP_GD_OCT          0xFFC22270         /* EMAC1 Number of bytes received in good UDP segments */
+#define EMAC1_RXUDP_ERR_OCT         0xFFC22274         /* EMAC1 Number of bytes received in UDP segment with checksum err */
+#define EMAC1_RXTCP_GD_OCT          0xFFC22278         /* EMAC1 Number of bytes received in a good TCP segment */
+#define EMAC1_RXTCP_ERR_OCT         0xFFC2227C         /* EMAC1 Number of bytes received in TCP segment with checksum err */
+#define EMAC1_RXICMP_GD_OCT         0xFFC22280         /* EMAC1 Number of bytes received in a good ICMP segment */
+#define EMAC1_RXICMP_ERR_OCT        0xFFC22284         /* EMAC1 Bytes received in an ICMP segment with checksum errors */
+#define EMAC1_TM_CTL                0xFFC22700         /* EMAC1 EMAC Time Stamp Control Register */
+#define EMAC1_TM_SUBSEC             0xFFC22704         /* EMAC1 EMAC Time Stamp Sub Second Increment */
+#define EMAC1_TM_SEC                0xFFC22708         /* EMAC1 EMAC Time Stamp Second Register */
+#define EMAC1_TM_NSEC               0xFFC2270C         /* EMAC1 EMAC Time Stamp Nano Second Register */
+#define EMAC1_TM_SECUPDT            0xFFC22710         /* EMAC1 EMAC Time Stamp Seconds Update */
+#define EMAC1_TM_NSECUPDT           0xFFC22714         /* EMAC1 EMAC Time Stamp Nano Seconds Update */
+#define EMAC1_TM_ADDEND             0xFFC22718         /* EMAC1 EMAC Time Stamp Addend Register */
+#define EMAC1_TM_TGTM               0xFFC2271C         /* EMAC1 EMAC Time Stamp Target Time Sec. */
+#define EMAC1_TM_NTGTM              0xFFC22720         /* EMAC1 EMAC Time Stamp Target Time Nanosec. */
+#define EMAC1_TM_HISEC              0xFFC22724         /* EMAC1 EMAC Time Stamp High Second Register */
+#define EMAC1_TM_STMPSTAT           0xFFC22728         /* EMAC1 EMAC Time Stamp Status Register */
+#define EMAC1_TM_PPSCTL             0xFFC2272C         /* EMAC1 EMAC PPS Control Register */
+#define EMAC1_TM_AUXSTMP_NSEC       0xFFC22730         /* EMAC1 EMAC Auxillary Time Stamp Nano Register */
+#define EMAC1_TM_AUXSTMP_SEC        0xFFC22734         /* EMAC1 EMAC Auxillary Time Stamp Sec Register */
+#define EMAC1_DMA_BUSMODE           0xFFC23000         /* EMAC1 Bus Operating Modes for EMAC DMA */
+#define EMAC1_DMA_TXPOLL            0xFFC23004         /* EMAC1 TX DMA Poll demand register */
+#define EMAC1_DMA_RXPOLL            0xFFC23008         /* EMAC1 RX DMA Poll demand register */
+#define EMAC1_DMA_RXDSC_ADDR        0xFFC2300C         /* EMAC1 RX Descriptor List Address */
+#define EMAC1_DMA_TXDSC_ADDR        0xFFC23010         /* EMAC1 TX Descriptor List Address */
+#define EMAC1_DMA_STAT              0xFFC23014         /* EMAC1 DMA Status Register */
+#define EMAC1_DMA_OPMODE            0xFFC23018         /* EMAC1 DMA Operation Mode Register */
+#define EMAC1_DMA_IEN               0xFFC2301C         /* EMAC1 DMA Interrupt Enable Register */
+#define EMAC1_DMA_MISS_FRM          0xFFC23020         /* EMAC1 DMA missed frame and buffer overflow counter */
+#define EMAC1_DMA_RXIWDOG           0xFFC23024         /* EMAC1 DMA RX Interrupt Watch Dog timer */
+#define EMAC1_DMA_BMMODE            0xFFC23028         /* EMAC1 AXI Bus Mode Register */
+#define EMAC1_DMA_BMSTAT            0xFFC2302C         /* EMAC1 AXI Status Register */
+#define EMAC1_DMA_TXDSC_CUR         0xFFC23048         /* EMAC1 TX current descriptor register */
+#define EMAC1_DMA_RXDSC_CUR         0xFFC2304C         /* EMAC1 RX current descriptor register */
+#define EMAC1_DMA_TXBUF_CUR         0xFFC23050         /* EMAC1 TX current buffer pointer register */
+#define EMAC1_DMA_RXBUF_CUR         0xFFC23054         /* EMAC1 RX current buffer pointer register */
+#define EMAC1_HWFEAT                0xFFC23058         /* EMAC1 Hardware Feature Register */
+#define SPORT0_CTL_A                0xFFC40000         /* SPORT0 'A' Control Register */
+#define SPORT0_DIV_A                0xFFC40004         /* SPORT0 'A' Clock and FS Divide Register */
+#define SPORT0_MCTL_A               0xFFC40008         /* SPORT0 'A' Multichannel Control Register */
+#define SPORT0_CS0_A                0xFFC4000C         /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */
+#define SPORT0_CS1_A                0xFFC40010         /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */
+#define SPORT0_CS2_A                0xFFC40014         /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */
+#define SPORT0_CS3_A                0xFFC40018         /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */
+#define SPORT0_CNT_A                0xFFC4001C         /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */
+#define SPORT0_ERR_A                0xFFC40020         /* SPORT0 'A' Error Register */
+#define SPORT0_MSTAT_A              0xFFC40024         /* SPORT0 'A' Multichannel Mode Status Register */
+#define SPORT0_CTL2_A               0xFFC40028         /* SPORT0 'A' Control Register 2 */
+#define SPORT0_TXPRI_A              0xFFC40040         /* SPORT0 'A' Primary Channel Transmit Buffer Register */
+#define SPORT0_RXPRI_A              0xFFC40044         /* SPORT0 'A' Primary Channel Receive Buffer Register */
+#define SPORT0_TXSEC_A              0xFFC40048         /* SPORT0 'A' Secondary Channel Transmit Buffer Register */
+#define SPORT0_RXSEC_A              0xFFC4004C         /* SPORT0 'A' Secondary Channel Receive Buffer Register */
+#define SPORT0_CTL_B                0xFFC40080         /* SPORT0 'B' Control Register */
+#define SPORT0_DIV_B                0xFFC40084         /* SPORT0 'B' Clock and FS Divide Register */
+#define SPORT0_MCTL_B               0xFFC40088         /* SPORT0 'B' Multichannel Control Register */
+#define SPORT0_CS0_B                0xFFC4008C         /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */
+#define SPORT0_CS1_B                0xFFC40090         /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */
+#define SPORT0_CS2_B                0xFFC40094         /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */
+#define SPORT0_CS3_B                0xFFC40098         /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */
+#define SPORT0_CNT_B                0xFFC4009C         /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */
+#define SPORT0_ERR_B                0xFFC400A0         /* SPORT0 'B' Error Register */
+#define SPORT0_MSTAT_B              0xFFC400A4         /* SPORT0 'B' Multichannel Mode Status Register */
+#define SPORT0_CTL2_B               0xFFC400A8         /* SPORT0 'B' Control Register 2 */
+#define SPORT0_TXPRI_B              0xFFC400C0         /* SPORT0 'B' Primary Channel Transmit Buffer Register */
+#define SPORT0_RXPRI_B              0xFFC400C4         /* SPORT0 'B' Primary Channel Receive Buffer Register */
+#define SPORT0_TXSEC_B              0xFFC400C8         /* SPORT0 'B' Secondary Channel Transmit Buffer Register */
+#define SPORT0_RXSEC_B              0xFFC400CC         /* SPORT0 'B' Secondary Channel Receive Buffer Register */
+#define SPORT1_CTL_A                0xFFC40100         /* SPORT1 'A' Control Register */
+#define SPORT1_DIV_A                0xFFC40104         /* SPORT1 'A' Clock and FS Divide Register */
+#define SPORT1_MCTL_A               0xFFC40108         /* SPORT1 'A' Multichannel Control Register */
+#define SPORT1_CS0_A                0xFFC4010C         /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */
+#define SPORT1_CS1_A                0xFFC40110         /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */
+#define SPORT1_CS2_A                0xFFC40114         /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */
+#define SPORT1_CS3_A                0xFFC40118         /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */
+#define SPORT1_CNT_A                0xFFC4011C         /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */
+#define SPORT1_ERR_A                0xFFC40120         /* SPORT1 'A' Error Register */
+#define SPORT1_MSTAT_A              0xFFC40124         /* SPORT1 'A' Multichannel Mode Status Register */
+#define SPORT1_CTL2_A               0xFFC40128         /* SPORT1 'A' Control Register 2 */
+#define SPORT1_TXPRI_A              0xFFC40140         /* SPORT1 'A' Primary Channel Transmit Buffer Register */
+#define SPORT1_RXPRI_A              0xFFC40144         /* SPORT1 'A' Primary Channel Receive Buffer Register */
+#define SPORT1_TXSEC_A              0xFFC40148         /* SPORT1 'A' Secondary Channel Transmit Buffer Register */
+#define SPORT1_RXSEC_A              0xFFC4014C         /* SPORT1 'A' Secondary Channel Receive Buffer Register */
+#define SPORT1_CTL_B                0xFFC40180         /* SPORT1 'B' Control Register */
+#define SPORT1_DIV_B                0xFFC40184         /* SPORT1 'B' Clock and FS Divide Register */
+#define SPORT1_MCTL_B               0xFFC40188         /* SPORT1 'B' Multichannel Control Register */
+#define SPORT1_CS0_B                0xFFC4018C         /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */
+#define SPORT1_CS1_B                0xFFC40190         /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */
+#define SPORT1_CS2_B                0xFFC40194         /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */
+#define SPORT1_CS3_B                0xFFC40198         /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */
+#define SPORT1_CNT_B                0xFFC4019C         /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */
+#define SPORT1_ERR_B                0xFFC401A0         /* SPORT1 'B' Error Register */
+#define SPORT1_MSTAT_B              0xFFC401A4         /* SPORT1 'B' Multichannel Mode Status Register */
+#define SPORT1_CTL2_B               0xFFC401A8         /* SPORT1 'B' Control Register 2 */
+#define SPORT1_TXPRI_B              0xFFC401C0         /* SPORT1 'B' Primary Channel Transmit Buffer Register */
+#define SPORT1_RXPRI_B              0xFFC401C4         /* SPORT1 'B' Primary Channel Receive Buffer Register */
+#define SPORT1_TXSEC_B              0xFFC401C8         /* SPORT1 'B' Secondary Channel Transmit Buffer Register */
+#define SPORT1_RXSEC_B              0xFFC401CC         /* SPORT1 'B' Secondary Channel Receive Buffer Register */
+#define SPORT2_CTL_A                0xFFC40200         /* SPORT2 'A' Control Register */
+#define SPORT2_DIV_A                0xFFC40204         /* SPORT2 'A' Clock and FS Divide Register */
+#define SPORT2_MCTL_A               0xFFC40208         /* SPORT2 'A' Multichannel Control Register */
+#define SPORT2_CS0_A                0xFFC4020C         /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */
+#define SPORT2_CS1_A                0xFFC40210         /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */
+#define SPORT2_CS2_A                0xFFC40214         /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */
+#define SPORT2_CS3_A                0xFFC40218         /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */
+#define SPORT2_CNT_A                0xFFC4021C         /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */
+#define SPORT2_ERR_A                0xFFC40220         /* SPORT2 'A' Error Register */
+#define SPORT2_MSTAT_A              0xFFC40224         /* SPORT2 'A' Multichannel Mode Status Register */
+#define SPORT2_CTL2_A               0xFFC40228         /* SPORT2 'A' Control Register 2 */
+#define SPORT2_TXPRI_A              0xFFC40240         /* SPORT2 'A' Primary Channel Transmit Buffer Register */
+#define SPORT2_RXPRI_A              0xFFC40244         /* SPORT2 'A' Primary Channel Receive Buffer Register */
+#define SPORT2_TXSEC_A              0xFFC40248         /* SPORT2 'A' Secondary Channel Transmit Buffer Register */
+#define SPORT2_RXSEC_A              0xFFC4024C         /* SPORT2 'A' Secondary Channel Receive Buffer Register */
+#define SPORT2_CTL_B                0xFFC40280         /* SPORT2 'B' Control Register */
+#define SPORT2_DIV_B                0xFFC40284         /* SPORT2 'B' Clock and FS Divide Register */
+#define SPORT2_MCTL_B               0xFFC40288         /* SPORT2 'B' Multichannel Control Register */
+#define SPORT2_CS0_B                0xFFC4028C         /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */
+#define SPORT2_CS1_B                0xFFC40290         /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */
+#define SPORT2_CS2_B                0xFFC40294         /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */
+#define SPORT2_CS3_B                0xFFC40298         /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */
+#define SPORT2_CNT_B                0xFFC4029C         /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */
+#define SPORT2_ERR_B                0xFFC402A0         /* SPORT2 'B' Error Register */
+#define SPORT2_MSTAT_B              0xFFC402A4         /* SPORT2 'B' Multichannel Mode Status Register */
+#define SPORT2_CTL2_B               0xFFC402A8         /* SPORT2 'B' Control Register 2 */
+#define SPORT2_TXPRI_B              0xFFC402C0         /* SPORT2 'B' Primary Channel Transmit Buffer Register */
+#define SPORT2_RXPRI_B              0xFFC402C4         /* SPORT2 'B' Primary Channel Receive Buffer Register */
+#define SPORT2_TXSEC_B              0xFFC402C8         /* SPORT2 'B' Secondary Channel Transmit Buffer Register */
+#define SPORT2_RXSEC_B              0xFFC402CC         /* SPORT2 'B' Secondary Channel Receive Buffer Register */
+#define SPI0_REGBASE                0xFFC40400
+#define SPI0_CTL                    0xFFC40404         /* SPI0 Control Register */
+#define SPI0_RXCTL                  0xFFC40408         /* SPI0 RX Control Register */
+#define SPI0_TXCTL                  0xFFC4040C         /* SPI0 TX Control Register */
+#define SPI0_CLK                    0xFFC40410         /* SPI0 Clock Rate Register */
+#define SPI0_DLY                    0xFFC40414         /* SPI0 Delay Register */
+#define SPI0_SLVSEL                 0xFFC40418         /* SPI0 Slave Select Register */
+#define SPI0_RWC                    0xFFC4041C         /* SPI0 Received Word-Count Register */
+#define SPI0_RWCR                   0xFFC40420         /* SPI0 Received Word-Count Reload Register */
+#define SPI0_TWC                    0xFFC40424         /* SPI0 Transmitted Word-Count Register */
+#define SPI0_TWCR                   0xFFC40428         /* SPI0 Transmitted Word-Count Reload Register */
+#define SPI0_IMSK                   0xFFC40430         /* SPI0 Interrupt Mask Register */
+#define SPI0_IMSK_CLR               0xFFC40434         /* SPI0 Interrupt Mask Clear Register */
+#define SPI0_IMSK_SET               0xFFC40438         /* SPI0 Interrupt Mask Set Register */
+#define SPI0_STAT                   0xFFC40440         /* SPI0 Status Register */
+#define SPI0_ILAT                   0xFFC40444         /* SPI0 Masked Interrupt Condition Register */
+#define SPI0_ILAT_CLR               0xFFC40448         /* SPI0 Masked Interrupt Clear Register */
+#define SPI0_RFIFO                  0xFFC40450         /* SPI0 Receive FIFO Data Register */
+#define SPI0_TFIFO                  0xFFC40458         /* SPI0 Transmit FIFO Data Register */
+#define SPI1_REGBASE                0xFFC40500
+#define SPI1_CTL                    0xFFC40504         /* SPI1 Control Register */
+#define SPI1_RXCTL                  0xFFC40508         /* SPI1 RX Control Register */
+#define SPI1_TXCTL                  0xFFC4050C         /* SPI1 TX Control Register */
+#define SPI1_CLK                    0xFFC40510         /* SPI1 Clock Rate Register */
+#define SPI1_DLY                    0xFFC40514         /* SPI1 Delay Register */
+#define SPI1_SLVSEL                 0xFFC40518         /* SPI1 Slave Select Register */
+#define SPI1_RWC                    0xFFC4051C         /* SPI1 Received Word-Count Register */
+#define SPI1_RWCR                   0xFFC40520         /* SPI1 Received Word-Count Reload Register */
+#define SPI1_TWC                    0xFFC40524         /* SPI1 Transmitted Word-Count Register */
+#define SPI1_TWCR                   0xFFC40528         /* SPI1 Transmitted Word-Count Reload Register */
+#define SPI1_IMSK                   0xFFC40530         /* SPI1 Interrupt Mask Register */
+#define SPI1_IMSK_CLR               0xFFC40534         /* SPI1 Interrupt Mask Clear Register */
+#define SPI1_IMSK_SET               0xFFC40538         /* SPI1 Interrupt Mask Set Register */
+#define SPI1_STAT                   0xFFC40540         /* SPI1 Status Register */
+#define SPI1_ILAT                   0xFFC40544         /* SPI1 Masked Interrupt Condition Register */
+#define SPI1_ILAT_CLR               0xFFC40548         /* SPI1 Masked Interrupt Clear Register */
+#define SPI1_RFIFO                  0xFFC40550         /* SPI1 Receive FIFO Data Register */
+#define SPI1_TFIFO                  0xFFC40558         /* SPI1 Transmit FIFO Data Register */
+#define DMA0_DSCPTR_NXT             0xFFC41000         /* DMA0 Pointer to Next Initial Descriptor */
+#define DMA0_ADDRSTART              0xFFC41004         /* DMA0 Start Address of Current Buffer */
+#define DMA0_CFG                    0xFFC41008         /* DMA0 Configuration Register */
+#define DMA0_XCNT                   0xFFC4100C         /* DMA0 Inner Loop Count Start Value */
+#define DMA0_XMOD                   0xFFC41010         /* DMA0 Inner Loop Address Increment */
+#define DMA0_YCNT                   0xFFC41014         /* DMA0 Outer Loop Count Start Value (2D only) */
+#define DMA0_YMOD                   0xFFC41018         /* DMA0 Outer Loop Address Increment (2D only) */
+#define DMA0_DSCPTR_CUR             0xFFC41024         /* DMA0 Current Descriptor Pointer */
+#define DMA0_DSCPTR_PRV             0xFFC41028         /* DMA0 Previous Initial Descriptor Pointer */
+#define DMA0_ADDR_CUR               0xFFC4102C         /* DMA0 Current Address */
+#define DMA0_STAT                   0xFFC41030         /* DMA0 Status Register */
+#define DMA0_XCNT_CUR               0xFFC41034         /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA0_YCNT_CUR               0xFFC41038         /* DMA0 Current Row Count (2D only) */
+#define DMA0_BWLCNT                 0xFFC41040         /* DMA0 Bandwidth Limit Count */
+#define DMA0_BWLCNT_CUR             0xFFC41044         /* DMA0 Bandwidth Limit Count Current */
+#define DMA0_BWMCNT                 0xFFC41048         /* DMA0 Bandwidth Monitor Count */
+#define DMA0_BWMCNT_CUR             0xFFC4104C         /* DMA0 Bandwidth Monitor Count Current */
+#define DMA1_DSCPTR_NXT             0xFFC41080         /* DMA1 Pointer to Next Initial Descriptor */
+#define DMA1_ADDRSTART              0xFFC41084         /* DMA1 Start Address of Current Buffer */
+#define DMA1_CFG                    0xFFC41088         /* DMA1 Configuration Register */
+#define DMA1_XCNT                   0xFFC4108C         /* DMA1 Inner Loop Count Start Value */
+#define DMA1_XMOD                   0xFFC41090         /* DMA1 Inner Loop Address Increment */
+#define DMA1_YCNT                   0xFFC41094         /* DMA1 Outer Loop Count Start Value (2D only) */
+#define DMA1_YMOD                   0xFFC41098         /* DMA1 Outer Loop Address Increment (2D only) */
+#define DMA1_DSCPTR_CUR             0xFFC410A4         /* DMA1 Current Descriptor Pointer */
+#define DMA1_DSCPTR_PRV             0xFFC410A8         /* DMA1 Previous Initial Descriptor Pointer */
+#define DMA1_ADDR_CUR               0xFFC410AC         /* DMA1 Current Address */
+#define DMA1_STAT                   0xFFC410B0         /* DMA1 Status Register */
+#define DMA1_XCNT_CUR               0xFFC410B4         /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA1_YCNT_CUR               0xFFC410B8         /* DMA1 Current Row Count (2D only) */
+#define DMA1_BWLCNT                 0xFFC410C0         /* DMA1 Bandwidth Limit Count */
+#define DMA1_BWLCNT_CUR             0xFFC410C4         /* DMA1 Bandwidth Limit Count Current */
+#define DMA1_BWMCNT                 0xFFC410C8         /* DMA1 Bandwidth Monitor Count */
+#define DMA1_BWMCNT_CUR             0xFFC410CC         /* DMA1 Bandwidth Monitor Count Current */
+#define DMA2_DSCPTR_NXT             0xFFC41100         /* DMA2 Pointer to Next Initial Descriptor */
+#define DMA2_ADDRSTART              0xFFC41104         /* DMA2 Start Address of Current Buffer */
+#define DMA2_CFG                    0xFFC41108         /* DMA2 Configuration Register */
+#define DMA2_XCNT                   0xFFC4110C         /* DMA2 Inner Loop Count Start Value */
+#define DMA2_XMOD                   0xFFC41110         /* DMA2 Inner Loop Address Increment */
+#define DMA2_YCNT                   0xFFC41114         /* DMA2 Outer Loop Count Start Value (2D only) */
+#define DMA2_YMOD                   0xFFC41118         /* DMA2 Outer Loop Address Increment (2D only) */
+#define DMA2_DSCPTR_CUR             0xFFC41124         /* DMA2 Current Descriptor Pointer */
+#define DMA2_DSCPTR_PRV             0xFFC41128         /* DMA2 Previous Initial Descriptor Pointer */
+#define DMA2_ADDR_CUR               0xFFC4112C         /* DMA2 Current Address */
+#define DMA2_STAT                   0xFFC41130         /* DMA2 Status Register */
+#define DMA2_XCNT_CUR               0xFFC41134         /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA2_YCNT_CUR               0xFFC41138         /* DMA2 Current Row Count (2D only) */
+#define DMA2_BWLCNT                 0xFFC41140         /* DMA2 Bandwidth Limit Count */
+#define DMA2_BWLCNT_CUR             0xFFC41144         /* DMA2 Bandwidth Limit Count Current */
+#define DMA2_BWMCNT                 0xFFC41148         /* DMA2 Bandwidth Monitor Count */
+#define DMA2_BWMCNT_CUR             0xFFC4114C         /* DMA2 Bandwidth Monitor Count Current */
+#define DMA3_DSCPTR_NXT             0xFFC41180         /* DMA3 Pointer to Next Initial Descriptor */
+#define DMA3_ADDRSTART              0xFFC41184         /* DMA3 Start Address of Current Buffer */
+#define DMA3_CFG                    0xFFC41188         /* DMA3 Configuration Register */
+#define DMA3_XCNT                   0xFFC4118C         /* DMA3 Inner Loop Count Start Value */
+#define DMA3_XMOD                   0xFFC41190         /* DMA3 Inner Loop Address Increment */
+#define DMA3_YCNT                   0xFFC41194         /* DMA3 Outer Loop Count Start Value (2D only) */
+#define DMA3_YMOD                   0xFFC41198         /* DMA3 Outer Loop Address Increment (2D only) */
+#define DMA3_DSCPTR_CUR             0xFFC411A4         /* DMA3 Current Descriptor Pointer */
+#define DMA3_DSCPTR_PRV             0xFFC411A8         /* DMA3 Previous Initial Descriptor Pointer */
+#define DMA3_ADDR_CUR               0xFFC411AC         /* DMA3 Current Address */
+#define DMA3_STAT                   0xFFC411B0         /* DMA3 Status Register */
+#define DMA3_XCNT_CUR               0xFFC411B4         /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA3_YCNT_CUR               0xFFC411B8         /* DMA3 Current Row Count (2D only) */
+#define DMA3_BWLCNT                 0xFFC411C0         /* DMA3 Bandwidth Limit Count */
+#define DMA3_BWLCNT_CUR             0xFFC411C4         /* DMA3 Bandwidth Limit Count Current */
+#define DMA3_BWMCNT                 0xFFC411C8         /* DMA3 Bandwidth Monitor Count */
+#define DMA3_BWMCNT_CUR             0xFFC411CC         /* DMA3 Bandwidth Monitor Count Current */
+#define DMA4_DSCPTR_NXT             0xFFC41200         /* DMA4 Pointer to Next Initial Descriptor */
+#define DMA4_ADDRSTART              0xFFC41204         /* DMA4 Start Address of Current Buffer */
+#define DMA4_CFG                    0xFFC41208         /* DMA4 Configuration Register */
+#define DMA4_XCNT                   0xFFC4120C         /* DMA4 Inner Loop Count Start Value */
+#define DMA4_XMOD                   0xFFC41210         /* DMA4 Inner Loop Address Increment */
+#define DMA4_YCNT                   0xFFC41214         /* DMA4 Outer Loop Count Start Value (2D only) */
+#define DMA4_YMOD                   0xFFC41218         /* DMA4 Outer Loop Address Increment (2D only) */
+#define DMA4_DSCPTR_CUR             0xFFC41224         /* DMA4 Current Descriptor Pointer */
+#define DMA4_DSCPTR_PRV             0xFFC41228         /* DMA4 Previous Initial Descriptor Pointer */
+#define DMA4_ADDR_CUR               0xFFC4122C         /* DMA4 Current Address */
+#define DMA4_STAT                   0xFFC41230         /* DMA4 Status Register */
+#define DMA4_XCNT_CUR               0xFFC41234         /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA4_YCNT_CUR               0xFFC41238         /* DMA4 Current Row Count (2D only) */
+#define DMA4_BWLCNT                 0xFFC41240         /* DMA4 Bandwidth Limit Count */
+#define DMA4_BWLCNT_CUR             0xFFC41244         /* DMA4 Bandwidth Limit Count Current */
+#define DMA4_BWMCNT                 0xFFC41248         /* DMA4 Bandwidth Monitor Count */
+#define DMA4_BWMCNT_CUR             0xFFC4124C         /* DMA4 Bandwidth Monitor Count Current */
+#define DMA5_DSCPTR_NXT             0xFFC41280         /* DMA5 Pointer to Next Initial Descriptor */
+#define DMA5_ADDRSTART              0xFFC41284         /* DMA5 Start Address of Current Buffer */
+#define DMA5_CFG                    0xFFC41288         /* DMA5 Configuration Register */
+#define DMA5_XCNT                   0xFFC4128C         /* DMA5 Inner Loop Count Start Value */
+#define DMA5_XMOD                   0xFFC41290         /* DMA5 Inner Loop Address Increment */
+#define DMA5_YCNT                   0xFFC41294         /* DMA5 Outer Loop Count Start Value (2D only) */
+#define DMA5_YMOD                   0xFFC41298         /* DMA5 Outer Loop Address Increment (2D only) */
+#define DMA5_DSCPTR_CUR             0xFFC412A4         /* DMA5 Current Descriptor Pointer */
+#define DMA5_DSCPTR_PRV             0xFFC412A8         /* DMA5 Previous Initial Descriptor Pointer */
+#define DMA5_ADDR_CUR               0xFFC412AC         /* DMA5 Current Address */
+#define DMA5_STAT                   0xFFC412B0         /* DMA5 Status Register */
+#define DMA5_XCNT_CUR               0xFFC412B4         /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA5_YCNT_CUR               0xFFC412B8         /* DMA5 Current Row Count (2D only) */
+#define DMA5_BWLCNT                 0xFFC412C0         /* DMA5 Bandwidth Limit Count */
+#define DMA5_BWLCNT_CUR             0xFFC412C4         /* DMA5 Bandwidth Limit Count Current */
+#define DMA5_BWMCNT                 0xFFC412C8         /* DMA5 Bandwidth Monitor Count */
+#define DMA5_BWMCNT_CUR             0xFFC412CC         /* DMA5 Bandwidth Monitor Count Current */
+#define DMA6_DSCPTR_NXT             0xFFC41300         /* DMA6 Pointer to Next Initial Descriptor */
+#define DMA6_ADDRSTART              0xFFC41304         /* DMA6 Start Address of Current Buffer */
+#define DMA6_CFG                    0xFFC41308         /* DMA6 Configuration Register */
+#define DMA6_XCNT                   0xFFC4130C         /* DMA6 Inner Loop Count Start Value */
+#define DMA6_XMOD                   0xFFC41310         /* DMA6 Inner Loop Address Increment */
+#define DMA6_YCNT                   0xFFC41314         /* DMA6 Outer Loop Count Start Value (2D only) */
+#define DMA6_YMOD                   0xFFC41318         /* DMA6 Outer Loop Address Increment (2D only) */
+#define DMA6_DSCPTR_CUR             0xFFC41324         /* DMA6 Current Descriptor Pointer */
+#define DMA6_DSCPTR_PRV             0xFFC41328         /* DMA6 Previous Initial Descriptor Pointer */
+#define DMA6_ADDR_CUR               0xFFC4132C         /* DMA6 Current Address */
+#define DMA6_STAT                   0xFFC41330         /* DMA6 Status Register */
+#define DMA6_XCNT_CUR               0xFFC41334         /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA6_YCNT_CUR               0xFFC41338         /* DMA6 Current Row Count (2D only) */
+#define DMA6_BWLCNT                 0xFFC41340         /* DMA6 Bandwidth Limit Count */
+#define DMA6_BWLCNT_CUR             0xFFC41344         /* DMA6 Bandwidth Limit Count Current */
+#define DMA6_BWMCNT                 0xFFC41348         /* DMA6 Bandwidth Monitor Count */
+#define DMA6_BWMCNT_CUR             0xFFC4134C         /* DMA6 Bandwidth Monitor Count Current */
+#define DMA7_DSCPTR_NXT             0xFFC41380         /* DMA7 Pointer to Next Initial Descriptor */
+#define DMA7_ADDRSTART              0xFFC41384         /* DMA7 Start Address of Current Buffer */
+#define DMA7_CFG                    0xFFC41388         /* DMA7 Configuration Register */
+#define DMA7_XCNT                   0xFFC4138C         /* DMA7 Inner Loop Count Start Value */
+#define DMA7_XMOD                   0xFFC41390         /* DMA7 Inner Loop Address Increment */
+#define DMA7_YCNT                   0xFFC41394         /* DMA7 Outer Loop Count Start Value (2D only) */
+#define DMA7_YMOD                   0xFFC41398         /* DMA7 Outer Loop Address Increment (2D only) */
+#define DMA7_DSCPTR_CUR             0xFFC413A4         /* DMA7 Current Descriptor Pointer */
+#define DMA7_DSCPTR_PRV             0xFFC413A8         /* DMA7 Previous Initial Descriptor Pointer */
+#define DMA7_ADDR_CUR               0xFFC413AC         /* DMA7 Current Address */
+#define DMA7_STAT                   0xFFC413B0         /* DMA7 Status Register */
+#define DMA7_XCNT_CUR               0xFFC413B4         /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA7_YCNT_CUR               0xFFC413B8         /* DMA7 Current Row Count (2D only) */
+#define DMA7_BWLCNT                 0xFFC413C0         /* DMA7 Bandwidth Limit Count */
+#define DMA7_BWLCNT_CUR             0xFFC413C4         /* DMA7 Bandwidth Limit Count Current */
+#define DMA7_BWMCNT                 0xFFC413C8         /* DMA7 Bandwidth Monitor Count */
+#define DMA7_BWMCNT_CUR             0xFFC413CC         /* DMA7 Bandwidth Monitor Count Current */
+#define DMA8_DSCPTR_NXT             0xFFC41400         /* DMA8 Pointer to Next Initial Descriptor */
+#define DMA8_ADDRSTART              0xFFC41404         /* DMA8 Start Address of Current Buffer */
+#define DMA8_CFG                    0xFFC41408         /* DMA8 Configuration Register */
+#define DMA8_XCNT                   0xFFC4140C         /* DMA8 Inner Loop Count Start Value */
+#define DMA8_XMOD                   0xFFC41410         /* DMA8 Inner Loop Address Increment */
+#define DMA8_YCNT                   0xFFC41414         /* DMA8 Outer Loop Count Start Value (2D only) */
+#define DMA8_YMOD                   0xFFC41418         /* DMA8 Outer Loop Address Increment (2D only) */
+#define DMA8_DSCPTR_CUR             0xFFC41424         /* DMA8 Current Descriptor Pointer */
+#define DMA8_DSCPTR_PRV             0xFFC41428         /* DMA8 Previous Initial Descriptor Pointer */
+#define DMA8_ADDR_CUR               0xFFC4142C         /* DMA8 Current Address */
+#define DMA8_STAT                   0xFFC41430         /* DMA8 Status Register */
+#define DMA8_XCNT_CUR               0xFFC41434         /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA8_YCNT_CUR               0xFFC41438         /* DMA8 Current Row Count (2D only) */
+#define DMA8_BWLCNT                 0xFFC41440         /* DMA8 Bandwidth Limit Count */
+#define DMA8_BWLCNT_CUR             0xFFC41444         /* DMA8 Bandwidth Limit Count Current */
+#define DMA8_BWMCNT                 0xFFC41448         /* DMA8 Bandwidth Monitor Count */
+#define DMA8_BWMCNT_CUR             0xFFC4144C         /* DMA8 Bandwidth Monitor Count Current */
+#define DMA9_DSCPTR_NXT             0xFFC41480         /* DMA9 Pointer to Next Initial Descriptor */
+#define DMA9_ADDRSTART              0xFFC41484         /* DMA9 Start Address of Current Buffer */
+#define DMA9_CFG                    0xFFC41488         /* DMA9 Configuration Register */
+#define DMA9_XCNT                   0xFFC4148C         /* DMA9 Inner Loop Count Start Value */
+#define DMA9_XMOD                   0xFFC41490         /* DMA9 Inner Loop Address Increment */
+#define DMA9_YCNT                   0xFFC41494         /* DMA9 Outer Loop Count Start Value (2D only) */
+#define DMA9_YMOD                   0xFFC41498         /* DMA9 Outer Loop Address Increment (2D only) */
+#define DMA9_DSCPTR_CUR             0xFFC414A4         /* DMA9 Current Descriptor Pointer */
+#define DMA9_DSCPTR_PRV             0xFFC414A8         /* DMA9 Previous Initial Descriptor Pointer */
+#define DMA9_ADDR_CUR               0xFFC414AC         /* DMA9 Current Address */
+#define DMA9_STAT                   0xFFC414B0         /* DMA9 Status Register */
+#define DMA9_XCNT_CUR               0xFFC414B4         /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA9_YCNT_CUR               0xFFC414B8         /* DMA9 Current Row Count (2D only) */
+#define DMA9_BWLCNT                 0xFFC414C0         /* DMA9 Bandwidth Limit Count */
+#define DMA9_BWLCNT_CUR             0xFFC414C4         /* DMA9 Bandwidth Limit Count Current */
+#define DMA9_BWMCNT                 0xFFC414C8         /* DMA9 Bandwidth Monitor Count */
+#define DMA9_BWMCNT_CUR             0xFFC414CC         /* DMA9 Bandwidth Monitor Count Current */
+#define DMA10_DSCPTR_NXT            0xFFC05000         /* DMA10 Pointer to Next Initial Descriptor */
+#define DMA10_ADDRSTART             0xFFC05004         /* DMA10 Start Address of Current Buffer */
+#define DMA10_CFG                   0xFFC05008         /* DMA10 Configuration Register */
+#define DMA10_XCNT                  0xFFC0500C         /* DMA10 Inner Loop Count Start Value */
+#define DMA10_XMOD                  0xFFC05010         /* DMA10 Inner Loop Address Increment */
+#define DMA10_YCNT                  0xFFC05014         /* DMA10 Outer Loop Count Start Value (2D only) */
+#define DMA10_YMOD                  0xFFC05018         /* DMA10 Outer Loop Address Increment (2D only) */
+#define DMA10_DSCPTR_CUR            0xFFC05024         /* DMA10 Current Descriptor Pointer */
+#define DMA10_DSCPTR_PRV            0xFFC05028         /* DMA10 Previous Initial Descriptor Pointer */
+#define DMA10_ADDR_CUR              0xFFC0502C         /* DMA10 Current Address */
+#define DMA10_STAT                  0xFFC05030         /* DMA10 Status Register */
+#define DMA10_XCNT_CUR              0xFFC05034         /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA10_YCNT_CUR              0xFFC05038         /* DMA10 Current Row Count (2D only) */
+#define DMA10_BWLCNT                0xFFC05040         /* DMA10 Bandwidth Limit Count */
+#define DMA10_BWLCNT_CUR            0xFFC05044         /* DMA10 Bandwidth Limit Count Current */
+#define DMA10_BWMCNT                0xFFC05048         /* DMA10 Bandwidth Monitor Count */
+#define DMA10_BWMCNT_CUR            0xFFC0504C         /* DMA10 Bandwidth Monitor Count Current */
+#define DMA11_DSCPTR_NXT            0xFFC05080         /* DMA11 Pointer to Next Initial Descriptor */
+#define DMA11_ADDRSTART             0xFFC05084         /* DMA11 Start Address of Current Buffer */
+#define DMA11_CFG                   0xFFC05088         /* DMA11 Configuration Register */
+#define DMA11_XCNT                  0xFFC0508C         /* DMA11 Inner Loop Count Start Value */
+#define DMA11_XMOD                  0xFFC05090         /* DMA11 Inner Loop Address Increment */
+#define DMA11_YCNT                  0xFFC05094         /* DMA11 Outer Loop Count Start Value (2D only) */
+#define DMA11_YMOD                  0xFFC05098         /* DMA11 Outer Loop Address Increment (2D only) */
+#define DMA11_DSCPTR_CUR            0xFFC050A4         /* DMA11 Current Descriptor Pointer */
+#define DMA11_DSCPTR_PRV            0xFFC050A8         /* DMA11 Previous Initial Descriptor Pointer */
+#define DMA11_ADDR_CUR              0xFFC050AC         /* DMA11 Current Address */
+#define DMA11_STAT                  0xFFC050B0         /* DMA11 Status Register */
+#define DMA11_XCNT_CUR              0xFFC050B4         /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA11_YCNT_CUR              0xFFC050B8         /* DMA11 Current Row Count (2D only) */
+#define DMA11_BWLCNT                0xFFC050C0         /* DMA11 Bandwidth Limit Count */
+#define DMA11_BWLCNT_CUR            0xFFC050C4         /* DMA11 Bandwidth Limit Count Current */
+#define DMA11_BWMCNT                0xFFC050C8         /* DMA11 Bandwidth Monitor Count */
+#define DMA11_BWMCNT_CUR            0xFFC050CC         /* DMA11 Bandwidth Monitor Count Current */
+#define DMA12_DSCPTR_NXT            0xFFC05100         /* DMA12 Pointer to Next Initial Descriptor */
+#define DMA12_ADDRSTART             0xFFC05104         /* DMA12 Start Address of Current Buffer */
+#define DMA12_CFG                   0xFFC05108         /* DMA12 Configuration Register */
+#define DMA12_XCNT                  0xFFC0510C         /* DMA12 Inner Loop Count Start Value */
+#define DMA12_XMOD                  0xFFC05110         /* DMA12 Inner Loop Address Increment */
+#define DMA12_YCNT                  0xFFC05114         /* DMA12 Outer Loop Count Start Value (2D only) */
+#define DMA12_YMOD                  0xFFC05118         /* DMA12 Outer Loop Address Increment (2D only) */
+#define DMA12_DSCPTR_CUR            0xFFC05124         /* DMA12 Current Descriptor Pointer */
+#define DMA12_DSCPTR_PRV            0xFFC05128         /* DMA12 Previous Initial Descriptor Pointer */
+#define DMA12_ADDR_CUR              0xFFC0512C         /* DMA12 Current Address */
+#define DMA12_STAT                  0xFFC05130         /* DMA12 Status Register */
+#define DMA12_XCNT_CUR              0xFFC05134         /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA12_YCNT_CUR              0xFFC05138         /* DMA12 Current Row Count (2D only) */
+#define DMA12_BWLCNT                0xFFC05140         /* DMA12 Bandwidth Limit Count */
+#define DMA12_BWLCNT_CUR            0xFFC05144         /* DMA12 Bandwidth Limit Count Current */
+#define DMA12_BWMCNT                0xFFC05148         /* DMA12 Bandwidth Monitor Count */
+#define DMA12_BWMCNT_CUR            0xFFC0514C         /* DMA12 Bandwidth Monitor Count Current */
+#define DMA13_DSCPTR_NXT            0xFFC07000         /* DMA13 Pointer to Next Initial Descriptor */
+#define DMA13_ADDRSTART             0xFFC07004         /* DMA13 Start Address of Current Buffer */
+#define DMA13_CFG                   0xFFC07008         /* DMA13 Configuration Register */
+#define DMA13_XCNT                  0xFFC0700C         /* DMA13 Inner Loop Count Start Value */
+#define DMA13_XMOD                  0xFFC07010         /* DMA13 Inner Loop Address Increment */
+#define DMA13_YCNT                  0xFFC07014         /* DMA13 Outer Loop Count Start Value (2D only) */
+#define DMA13_YMOD                  0xFFC07018         /* DMA13 Outer Loop Address Increment (2D only) */
+#define DMA13_DSCPTR_CUR            0xFFC07024         /* DMA13 Current Descriptor Pointer */
+#define DMA13_DSCPTR_PRV            0xFFC07028         /* DMA13 Previous Initial Descriptor Pointer */
+#define DMA13_ADDR_CUR              0xFFC0702C         /* DMA13 Current Address */
+#define DMA13_STAT                  0xFFC07030         /* DMA13 Status Register */
+#define DMA13_XCNT_CUR              0xFFC07034         /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA13_YCNT_CUR              0xFFC07038         /* DMA13 Current Row Count (2D only) */
+#define DMA13_BWLCNT                0xFFC07040         /* DMA13 Bandwidth Limit Count */
+#define DMA13_BWLCNT_CUR            0xFFC07044         /* DMA13 Bandwidth Limit Count Current */
+#define DMA13_BWMCNT                0xFFC07048         /* DMA13 Bandwidth Monitor Count */
+#define DMA13_BWMCNT_CUR            0xFFC0704C         /* DMA13 Bandwidth Monitor Count Current */
+#define DMA14_DSCPTR_NXT            0xFFC07080         /* DMA14 Pointer to Next Initial Descriptor */
+#define DMA14_ADDRSTART             0xFFC07084         /* DMA14 Start Address of Current Buffer */
+#define DMA14_CFG                   0xFFC07088         /* DMA14 Configuration Register */
+#define DMA14_XCNT                  0xFFC0708C         /* DMA14 Inner Loop Count Start Value */
+#define DMA14_XMOD                  0xFFC07090         /* DMA14 Inner Loop Address Increment */
+#define DMA14_YCNT                  0xFFC07094         /* DMA14 Outer Loop Count Start Value (2D only) */
+#define DMA14_YMOD                  0xFFC07098         /* DMA14 Outer Loop Address Increment (2D only) */
+#define DMA14_DSCPTR_CUR            0xFFC070A4         /* DMA14 Current Descriptor Pointer */
+#define DMA14_DSCPTR_PRV            0xFFC070A8         /* DMA14 Previous Initial Descriptor Pointer */
+#define DMA14_ADDR_CUR              0xFFC070AC         /* DMA14 Current Address */
+#define DMA14_STAT                  0xFFC070B0         /* DMA14 Status Register */
+#define DMA14_XCNT_CUR              0xFFC070B4         /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA14_YCNT_CUR              0xFFC070B8         /* DMA14 Current Row Count (2D only) */
+#define DMA14_BWLCNT                0xFFC070C0         /* DMA14 Bandwidth Limit Count */
+#define DMA14_BWLCNT_CUR            0xFFC070C4         /* DMA14 Bandwidth Limit Count Current */
+#define DMA14_BWMCNT                0xFFC070C8         /* DMA14 Bandwidth Monitor Count */
+#define DMA14_BWMCNT_CUR            0xFFC070CC         /* DMA14 Bandwidth Monitor Count Current */
+#define DMA15_DSCPTR_NXT            0xFFC07100         /* DMA15 Pointer to Next Initial Descriptor */
+#define DMA15_ADDRSTART             0xFFC07104         /* DMA15 Start Address of Current Buffer */
+#define DMA15_CFG                   0xFFC07108         /* DMA15 Configuration Register */
+#define DMA15_XCNT                  0xFFC0710C         /* DMA15 Inner Loop Count Start Value */
+#define DMA15_XMOD                  0xFFC07110         /* DMA15 Inner Loop Address Increment */
+#define DMA15_YCNT                  0xFFC07114         /* DMA15 Outer Loop Count Start Value (2D only) */
+#define DMA15_YMOD                  0xFFC07118         /* DMA15 Outer Loop Address Increment (2D only) */
+#define DMA15_DSCPTR_CUR            0xFFC07124         /* DMA15 Current Descriptor Pointer */
+#define DMA15_DSCPTR_PRV            0xFFC07128         /* DMA15 Previous Initial Descriptor Pointer */
+#define DMA15_ADDR_CUR              0xFFC0712C         /* DMA15 Current Address */
+#define DMA15_STAT                  0xFFC07130         /* DMA15 Status Register */
+#define DMA15_XCNT_CUR              0xFFC07134         /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA15_YCNT_CUR              0xFFC07138         /* DMA15 Current Row Count (2D only) */
+#define DMA15_BWLCNT                0xFFC07140         /* DMA15 Bandwidth Limit Count */
+#define DMA15_BWLCNT_CUR            0xFFC07144         /* DMA15 Bandwidth Limit Count Current */
+#define DMA15_BWMCNT                0xFFC07148         /* DMA15 Bandwidth Monitor Count */
+#define DMA15_BWMCNT_CUR            0xFFC0714C         /* DMA15 Bandwidth Monitor Count Current */
+#define DMA16_DSCPTR_NXT            0xFFC07180         /* DMA16 Pointer to Next Initial Descriptor */
+#define DMA16_ADDRSTART             0xFFC07184         /* DMA16 Start Address of Current Buffer */
+#define DMA16_CFG                   0xFFC07188         /* DMA16 Configuration Register */
+#define DMA16_XCNT                  0xFFC0718C         /* DMA16 Inner Loop Count Start Value */
+#define DMA16_XMOD                  0xFFC07190         /* DMA16 Inner Loop Address Increment */
+#define DMA16_YCNT                  0xFFC07194         /* DMA16 Outer Loop Count Start Value (2D only) */
+#define DMA16_YMOD                  0xFFC07198         /* DMA16 Outer Loop Address Increment (2D only) */
+#define DMA16_DSCPTR_CUR            0xFFC071A4         /* DMA16 Current Descriptor Pointer */
+#define DMA16_DSCPTR_PRV            0xFFC071A8         /* DMA16 Previous Initial Descriptor Pointer */
+#define DMA16_ADDR_CUR              0xFFC071AC         /* DMA16 Current Address */
+#define DMA16_STAT                  0xFFC071B0         /* DMA16 Status Register */
+#define DMA16_XCNT_CUR              0xFFC071B4         /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA16_YCNT_CUR              0xFFC071B8         /* DMA16 Current Row Count (2D only) */
+#define DMA16_BWLCNT                0xFFC071C0         /* DMA16 Bandwidth Limit Count */
+#define DMA16_BWLCNT_CUR            0xFFC071C4         /* DMA16 Bandwidth Limit Count Current */
+#define DMA16_BWMCNT                0xFFC071C8         /* DMA16 Bandwidth Monitor Count */
+#define DMA16_BWMCNT_CUR            0xFFC071CC         /* DMA16 Bandwidth Monitor Count Current */
+#define DMA17_DSCPTR_NXT            0xFFC07200         /* DMA17 Pointer to Next Initial Descriptor */
+#define DMA17_ADDRSTART             0xFFC07204         /* DMA17 Start Address of Current Buffer */
+#define DMA17_CFG                   0xFFC07208         /* DMA17 Configuration Register */
+#define DMA17_XCNT                  0xFFC0720C         /* DMA17 Inner Loop Count Start Value */
+#define DMA17_XMOD                  0xFFC07210         /* DMA17 Inner Loop Address Increment */
+#define DMA17_YCNT                  0xFFC07214         /* DMA17 Outer Loop Count Start Value (2D only) */
+#define DMA17_YMOD                  0xFFC07218         /* DMA17 Outer Loop Address Increment (2D only) */
+#define DMA17_DSCPTR_CUR            0xFFC07224         /* DMA17 Current Descriptor Pointer */
+#define DMA17_DSCPTR_PRV            0xFFC07228         /* DMA17 Previous Initial Descriptor Pointer */
+#define DMA17_ADDR_CUR              0xFFC0722C         /* DMA17 Current Address */
+#define DMA17_STAT                  0xFFC07230         /* DMA17 Status Register */
+#define DMA17_XCNT_CUR              0xFFC07234         /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA17_YCNT_CUR              0xFFC07238         /* DMA17 Current Row Count (2D only) */
+#define DMA17_BWLCNT                0xFFC07240         /* DMA17 Bandwidth Limit Count */
+#define DMA17_BWLCNT_CUR            0xFFC07244         /* DMA17 Bandwidth Limit Count Current */
+#define DMA17_BWMCNT                0xFFC07248         /* DMA17 Bandwidth Monitor Count */
+#define DMA17_BWMCNT_CUR            0xFFC0724C         /* DMA17 Bandwidth Monitor Count Current */
+#define DMA18_DSCPTR_NXT            0xFFC07280         /* DMA18 Pointer to Next Initial Descriptor */
+#define DMA18_ADDRSTART             0xFFC07284         /* DMA18 Start Address of Current Buffer */
+#define DMA18_CFG                   0xFFC07288         /* DMA18 Configuration Register */
+#define DMA18_XCNT                  0xFFC0728C         /* DMA18 Inner Loop Count Start Value */
+#define DMA18_XMOD                  0xFFC07290         /* DMA18 Inner Loop Address Increment */
+#define DMA18_YCNT                  0xFFC07294         /* DMA18 Outer Loop Count Start Value (2D only) */
+#define DMA18_YMOD                  0xFFC07298         /* DMA18 Outer Loop Address Increment (2D only) */
+#define DMA18_DSCPTR_CUR            0xFFC072A4         /* DMA18 Current Descriptor Pointer */
+#define DMA18_DSCPTR_PRV            0xFFC072A8         /* DMA18 Previous Initial Descriptor Pointer */
+#define DMA18_ADDR_CUR              0xFFC072AC         /* DMA18 Current Address */
+#define DMA18_STAT                  0xFFC072B0         /* DMA18 Status Register */
+#define DMA18_XCNT_CUR              0xFFC072B4         /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA18_YCNT_CUR              0xFFC072B8         /* DMA18 Current Row Count (2D only) */
+#define DMA18_BWLCNT                0xFFC072C0         /* DMA18 Bandwidth Limit Count */
+#define DMA18_BWLCNT_CUR            0xFFC072C4         /* DMA18 Bandwidth Limit Count Current */
+#define DMA18_BWMCNT                0xFFC072C8         /* DMA18 Bandwidth Monitor Count */
+#define DMA18_BWMCNT_CUR            0xFFC072CC         /* DMA18 Bandwidth Monitor Count Current */
+#define DMA19_DSCPTR_NXT            0xFFC07300         /* DMA19 Pointer to Next Initial Descriptor */
+#define DMA19_ADDRSTART             0xFFC07304         /* DMA19 Start Address of Current Buffer */
+#define DMA19_CFG                   0xFFC07308         /* DMA19 Configuration Register */
+#define DMA19_XCNT                  0xFFC0730C         /* DMA19 Inner Loop Count Start Value */
+#define DMA19_XMOD                  0xFFC07310         /* DMA19 Inner Loop Address Increment */
+#define DMA19_YCNT                  0xFFC07314         /* DMA19 Outer Loop Count Start Value (2D only) */
+#define DMA19_YMOD                  0xFFC07318         /* DMA19 Outer Loop Address Increment (2D only) */
+#define DMA19_DSCPTR_CUR            0xFFC07324         /* DMA19 Current Descriptor Pointer */
+#define DMA19_DSCPTR_PRV            0xFFC07328         /* DMA19 Previous Initial Descriptor Pointer */
+#define DMA19_ADDR_CUR              0xFFC0732C         /* DMA19 Current Address */
+#define DMA19_STAT                  0xFFC07330         /* DMA19 Status Register */
+#define DMA19_XCNT_CUR              0xFFC07334         /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA19_YCNT_CUR              0xFFC07338         /* DMA19 Current Row Count (2D only) */
+#define DMA19_BWLCNT                0xFFC07340         /* DMA19 Bandwidth Limit Count */
+#define DMA19_BWLCNT_CUR            0xFFC07344         /* DMA19 Bandwidth Limit Count Current */
+#define DMA19_BWMCNT                0xFFC07348         /* DMA19 Bandwidth Monitor Count */
+#define DMA19_BWMCNT_CUR            0xFFC0734C         /* DMA19 Bandwidth Monitor Count Current */
+#define DMA20_DSCPTR_NXT            0xFFC07380         /* DMA20 Pointer to Next Initial Descriptor */
+#define DMA20_ADDRSTART             0xFFC07384         /* DMA20 Start Address of Current Buffer */
+#define DMA20_CFG                   0xFFC07388         /* DMA20 Configuration Register */
+#define DMA20_XCNT                  0xFFC0738C         /* DMA20 Inner Loop Count Start Value */
+#define DMA20_XMOD                  0xFFC07390         /* DMA20 Inner Loop Address Increment */
+#define DMA20_YCNT                  0xFFC07394         /* DMA20 Outer Loop Count Start Value (2D only) */
+#define DMA20_YMOD                  0xFFC07398         /* DMA20 Outer Loop Address Increment (2D only) */
+#define DMA20_DSCPTR_CUR            0xFFC073A4         /* DMA20 Current Descriptor Pointer */
+#define DMA20_DSCPTR_PRV            0xFFC073A8         /* DMA20 Previous Initial Descriptor Pointer */
+#define DMA20_ADDR_CUR              0xFFC073AC         /* DMA20 Current Address */
+#define DMA20_STAT                  0xFFC073B0         /* DMA20 Status Register */
+#define DMA20_XCNT_CUR              0xFFC073B4         /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA20_YCNT_CUR              0xFFC073B8         /* DMA20 Current Row Count (2D only) */
+#define DMA20_BWLCNT                0xFFC073C0         /* DMA20 Bandwidth Limit Count */
+#define DMA20_BWLCNT_CUR            0xFFC073C4         /* DMA20 Bandwidth Limit Count Current */
+#define DMA20_BWMCNT                0xFFC073C8         /* DMA20 Bandwidth Monitor Count */
+#define DMA20_BWMCNT_CUR            0xFFC073CC         /* DMA20 Bandwidth Monitor Count Current */
+#define MDMA_S0_NEXT_DESC_PTR DMA21_DSCPTR_NXT
+#define DMA21_DSCPTR_NXT            0xFFC09000         /* DMA21 Pointer to Next Initial Descriptor */
+#define DMA21_ADDRSTART             0xFFC09004         /* DMA21 Start Address of Current Buffer */
+#define DMA21_CFG                   0xFFC09008         /* DMA21 Configuration Register */
+#define DMA21_XCNT                  0xFFC0900C         /* DMA21 Inner Loop Count Start Value */
+#define DMA21_XMOD                  0xFFC09010         /* DMA21 Inner Loop Address Increment */
+#define DMA21_YCNT                  0xFFC09014         /* DMA21 Outer Loop Count Start Value (2D only) */
+#define DMA21_YMOD                  0xFFC09018         /* DMA21 Outer Loop Address Increment (2D only) */
+#define DMA21_DSCPTR_CUR            0xFFC09024         /* DMA21 Current Descriptor Pointer */
+#define DMA21_DSCPTR_PRV            0xFFC09028         /* DMA21 Previous Initial Descriptor Pointer */
+#define DMA21_ADDR_CUR              0xFFC0902C         /* DMA21 Current Address */
+#define DMA21_STAT                  0xFFC09030         /* DMA21 Status Register */
+#define DMA21_XCNT_CUR              0xFFC09034         /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA21_YCNT_CUR              0xFFC09038         /* DMA21 Current Row Count (2D only) */
+#define DMA21_BWLCNT                0xFFC09040         /* DMA21 Bandwidth Limit Count */
+#define DMA21_BWLCNT_CUR            0xFFC09044         /* DMA21 Bandwidth Limit Count Current */
+#define DMA21_BWMCNT                0xFFC09048         /* DMA21 Bandwidth Monitor Count */
+#define DMA21_BWMCNT_CUR            0xFFC0904C         /* DMA21 Bandwidth Monitor Count Current */
+#define MDMA_D0_NEXT_DESC_PTR DMA22_DSCPTR_NXT
+#define DMA22_DSCPTR_NXT            0xFFC09080         /* DMA22 Pointer to Next Initial Descriptor */
+#define DMA22_ADDRSTART             0xFFC09084         /* DMA22 Start Address of Current Buffer */
+#define DMA22_CFG                   0xFFC09088         /* DMA22 Configuration Register */
+#define DMA22_XCNT                  0xFFC0908C         /* DMA22 Inner Loop Count Start Value */
+#define DMA22_XMOD                  0xFFC09090         /* DMA22 Inner Loop Address Increment */
+#define DMA22_YCNT                  0xFFC09094         /* DMA22 Outer Loop Count Start Value (2D only) */
+#define DMA22_YMOD                  0xFFC09098         /* DMA22 Outer Loop Address Increment (2D only) */
+#define DMA22_DSCPTR_CUR            0xFFC090A4         /* DMA22 Current Descriptor Pointer */
+#define DMA22_DSCPTR_PRV            0xFFC090A8         /* DMA22 Previous Initial Descriptor Pointer */
+#define DMA22_ADDR_CUR              0xFFC090AC         /* DMA22 Current Address */
+#define DMA22_STAT                  0xFFC090B0         /* DMA22 Status Register */
+#define DMA22_XCNT_CUR              0xFFC090B4         /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA22_YCNT_CUR              0xFFC090B8         /* DMA22 Current Row Count (2D only) */
+#define DMA22_BWLCNT                0xFFC090C0         /* DMA22 Bandwidth Limit Count */
+#define DMA22_BWLCNT_CUR            0xFFC090C4         /* DMA22 Bandwidth Limit Count Current */
+#define DMA22_BWMCNT                0xFFC090C8         /* DMA22 Bandwidth Monitor Count */
+#define DMA22_BWMCNT_CUR            0xFFC090CC         /* DMA22 Bandwidth Monitor Count Current */
+#define DMA23_DSCPTR_NXT            0xFFC09100         /* DMA23 Pointer to Next Initial Descriptor */
+#define DMA23_ADDRSTART             0xFFC09104         /* DMA23 Start Address of Current Buffer */
+#define DMA23_CFG                   0xFFC09108         /* DMA23 Configuration Register */
+#define DMA23_XCNT                  0xFFC0910C         /* DMA23 Inner Loop Count Start Value */
+#define DMA23_XMOD                  0xFFC09110         /* DMA23 Inner Loop Address Increment */
+#define DMA23_YCNT                  0xFFC09114         /* DMA23 Outer Loop Count Start Value (2D only) */
+#define DMA23_YMOD                  0xFFC09118         /* DMA23 Outer Loop Address Increment (2D only) */
+#define DMA23_DSCPTR_CUR            0xFFC09124         /* DMA23 Current Descriptor Pointer */
+#define DMA23_DSCPTR_PRV            0xFFC09128         /* DMA23 Previous Initial Descriptor Pointer */
+#define DMA23_ADDR_CUR              0xFFC0912C         /* DMA23 Current Address */
+#define DMA23_STAT                  0xFFC09130         /* DMA23 Status Register */
+#define DMA23_XCNT_CUR              0xFFC09134         /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA23_YCNT_CUR              0xFFC09138         /* DMA23 Current Row Count (2D only) */
+#define DMA23_BWLCNT                0xFFC09140         /* DMA23 Bandwidth Limit Count */
+#define DMA23_BWLCNT_CUR            0xFFC09144         /* DMA23 Bandwidth Limit Count Current */
+#define DMA23_BWMCNT                0xFFC09148         /* DMA23 Bandwidth Monitor Count */
+#define DMA23_BWMCNT_CUR            0xFFC0914C         /* DMA23 Bandwidth Monitor Count Current */
+#define DMA24_DSCPTR_NXT            0xFFC09180         /* DMA24 Pointer to Next Initial Descriptor */
+#define DMA24_ADDRSTART             0xFFC09184         /* DMA24 Start Address of Current Buffer */
+#define DMA24_CFG                   0xFFC09188         /* DMA24 Configuration Register */
+#define DMA24_XCNT                  0xFFC0918C         /* DMA24 Inner Loop Count Start Value */
+#define DMA24_XMOD                  0xFFC09190         /* DMA24 Inner Loop Address Increment */
+#define DMA24_YCNT                  0xFFC09194         /* DMA24 Outer Loop Count Start Value (2D only) */
+#define DMA24_YMOD                  0xFFC09198         /* DMA24 Outer Loop Address Increment (2D only) */
+#define DMA24_DSCPTR_CUR            0xFFC091A4         /* DMA24 Current Descriptor Pointer */
+#define DMA24_DSCPTR_PRV            0xFFC091A8         /* DMA24 Previous Initial Descriptor Pointer */
+#define DMA24_ADDR_CUR              0xFFC091AC         /* DMA24 Current Address */
+#define DMA24_STAT                  0xFFC091B0         /* DMA24 Status Register */
+#define DMA24_XCNT_CUR              0xFFC091B4         /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA24_YCNT_CUR              0xFFC091B8         /* DMA24 Current Row Count (2D only) */
+#define DMA24_BWLCNT                0xFFC091C0         /* DMA24 Bandwidth Limit Count */
+#define DMA24_BWLCNT_CUR            0xFFC091C4         /* DMA24 Bandwidth Limit Count Current */
+#define DMA24_BWMCNT                0xFFC091C8         /* DMA24 Bandwidth Monitor Count */
+#define DMA24_BWMCNT_CUR            0xFFC091CC         /* DMA24 Bandwidth Monitor Count Current */
+#define DMA25_DSCPTR_NXT            0xFFC09200         /* DMA25 Pointer to Next Initial Descriptor */
+#define DMA25_ADDRSTART             0xFFC09204         /* DMA25 Start Address of Current Buffer */
+#define DMA25_CFG                   0xFFC09208         /* DMA25 Configuration Register */
+#define DMA25_XCNT                  0xFFC0920C         /* DMA25 Inner Loop Count Start Value */
+#define DMA25_XMOD                  0xFFC09210         /* DMA25 Inner Loop Address Increment */
+#define DMA25_YCNT                  0xFFC09214         /* DMA25 Outer Loop Count Start Value (2D only) */
+#define DMA25_YMOD                  0xFFC09218         /* DMA25 Outer Loop Address Increment (2D only) */
+#define DMA25_DSCPTR_CUR            0xFFC09224         /* DMA25 Current Descriptor Pointer */
+#define DMA25_DSCPTR_PRV            0xFFC09228         /* DMA25 Previous Initial Descriptor Pointer */
+#define DMA25_ADDR_CUR              0xFFC0922C         /* DMA25 Current Address */
+#define DMA25_STAT                  0xFFC09230         /* DMA25 Status Register */
+#define DMA25_XCNT_CUR              0xFFC09234         /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA25_YCNT_CUR              0xFFC09238         /* DMA25 Current Row Count (2D only) */
+#define DMA25_BWLCNT                0xFFC09240         /* DMA25 Bandwidth Limit Count */
+#define DMA25_BWLCNT_CUR            0xFFC09244         /* DMA25 Bandwidth Limit Count Current */
+#define DMA25_BWMCNT                0xFFC09248         /* DMA25 Bandwidth Monitor Count */
+#define DMA25_BWMCNT_CUR            0xFFC0924C         /* DMA25 Bandwidth Monitor Count Current */
+#define DMA26_DSCPTR_NXT            0xFFC09280         /* DMA26 Pointer to Next Initial Descriptor */
+#define DMA26_ADDRSTART             0xFFC09284         /* DMA26 Start Address of Current Buffer */
+#define DMA26_CFG                   0xFFC09288         /* DMA26 Configuration Register */
+#define DMA26_XCNT                  0xFFC0928C         /* DMA26 Inner Loop Count Start Value */
+#define DMA26_XMOD                  0xFFC09290         /* DMA26 Inner Loop Address Increment */
+#define DMA26_YCNT                  0xFFC09294         /* DMA26 Outer Loop Count Start Value (2D only) */
+#define DMA26_YMOD                  0xFFC09298         /* DMA26 Outer Loop Address Increment (2D only) */
+#define DMA26_DSCPTR_CUR            0xFFC092A4         /* DMA26 Current Descriptor Pointer */
+#define DMA26_DSCPTR_PRV            0xFFC092A8         /* DMA26 Previous Initial Descriptor Pointer */
+#define DMA26_ADDR_CUR              0xFFC092AC         /* DMA26 Current Address */
+#define DMA26_STAT                  0xFFC092B0         /* DMA26 Status Register */
+#define DMA26_XCNT_CUR              0xFFC092B4         /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA26_YCNT_CUR              0xFFC092B8         /* DMA26 Current Row Count (2D only) */
+#define DMA26_BWLCNT                0xFFC092C0         /* DMA26 Bandwidth Limit Count */
+#define DMA26_BWLCNT_CUR            0xFFC092C4         /* DMA26 Bandwidth Limit Count Current */
+#define DMA26_BWMCNT                0xFFC092C8         /* DMA26 Bandwidth Monitor Count */
+#define DMA26_BWMCNT_CUR            0xFFC092CC         /* DMA26 Bandwidth Monitor Count Current */
+#define DMA27_DSCPTR_NXT            0xFFC09300         /* DMA27 Pointer to Next Initial Descriptor */
+#define DMA27_ADDRSTART             0xFFC09304         /* DMA27 Start Address of Current Buffer */
+#define DMA27_CFG                   0xFFC09308         /* DMA27 Configuration Register */
+#define DMA27_XCNT                  0xFFC0930C         /* DMA27 Inner Loop Count Start Value */
+#define DMA27_XMOD                  0xFFC09310         /* DMA27 Inner Loop Address Increment */
+#define DMA27_YCNT                  0xFFC09314         /* DMA27 Outer Loop Count Start Value (2D only) */
+#define DMA27_YMOD                  0xFFC09318         /* DMA27 Outer Loop Address Increment (2D only) */
+#define DMA27_DSCPTR_CUR            0xFFC09324         /* DMA27 Current Descriptor Pointer */
+#define DMA27_DSCPTR_PRV            0xFFC09328         /* DMA27 Previous Initial Descriptor Pointer */
+#define DMA27_ADDR_CUR              0xFFC0932C         /* DMA27 Current Address */
+#define DMA27_STAT                  0xFFC09330         /* DMA27 Status Register */
+#define DMA27_XCNT_CUR              0xFFC09334         /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA27_YCNT_CUR              0xFFC09338         /* DMA27 Current Row Count (2D only) */
+#define DMA27_BWLCNT                0xFFC09340         /* DMA27 Bandwidth Limit Count */
+#define DMA27_BWLCNT_CUR            0xFFC09344         /* DMA27 Bandwidth Limit Count Current */
+#define DMA27_BWMCNT                0xFFC09348         /* DMA27 Bandwidth Monitor Count */
+#define DMA27_BWMCNT_CUR            0xFFC0934C         /* DMA27 Bandwidth Monitor Count Current */
+#define DMA28_DSCPTR_NXT            0xFFC09380         /* DMA28 Pointer to Next Initial Descriptor */
+#define DMA28_ADDRSTART             0xFFC09384         /* DMA28 Start Address of Current Buffer */
+#define DMA28_CFG                   0xFFC09388         /* DMA28 Configuration Register */
+#define DMA28_XCNT                  0xFFC0938C         /* DMA28 Inner Loop Count Start Value */
+#define DMA28_XMOD                  0xFFC09390         /* DMA28 Inner Loop Address Increment */
+#define DMA28_YCNT                  0xFFC09394         /* DMA28 Outer Loop Count Start Value (2D only) */
+#define DMA28_YMOD                  0xFFC09398         /* DMA28 Outer Loop Address Increment (2D only) */
+#define DMA28_DSCPTR_CUR            0xFFC093A4         /* DMA28 Current Descriptor Pointer */
+#define DMA28_DSCPTR_PRV            0xFFC093A8         /* DMA28 Previous Initial Descriptor Pointer */
+#define DMA28_ADDR_CUR              0xFFC093AC         /* DMA28 Current Address */
+#define DMA28_STAT                  0xFFC093B0         /* DMA28 Status Register */
+#define DMA28_XCNT_CUR              0xFFC093B4         /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA28_YCNT_CUR              0xFFC093B8         /* DMA28 Current Row Count (2D only) */
+#define DMA28_BWLCNT                0xFFC093C0         /* DMA28 Bandwidth Limit Count */
+#define DMA28_BWLCNT_CUR            0xFFC093C4         /* DMA28 Bandwidth Limit Count Current */
+#define DMA28_BWMCNT                0xFFC093C8         /* DMA28 Bandwidth Monitor Count */
+#define DMA28_BWMCNT_CUR            0xFFC093CC         /* DMA28 Bandwidth Monitor Count Current */
+#define DMA29_DSCPTR_NXT            0xFFC0B000         /* DMA29 Pointer to Next Initial Descriptor */
+#define DMA29_ADDRSTART             0xFFC0B004         /* DMA29 Start Address of Current Buffer */
+#define DMA29_CFG                   0xFFC0B008         /* DMA29 Configuration Register */
+#define DMA29_XCNT                  0xFFC0B00C         /* DMA29 Inner Loop Count Start Value */
+#define DMA29_XMOD                  0xFFC0B010         /* DMA29 Inner Loop Address Increment */
+#define DMA29_YCNT                  0xFFC0B014         /* DMA29 Outer Loop Count Start Value (2D only) */
+#define DMA29_YMOD                  0xFFC0B018         /* DMA29 Outer Loop Address Increment (2D only) */
+#define DMA29_DSCPTR_CUR            0xFFC0B024         /* DMA29 Current Descriptor Pointer */
+#define DMA29_DSCPTR_PRV            0xFFC0B028         /* DMA29 Previous Initial Descriptor Pointer */
+#define DMA29_ADDR_CUR              0xFFC0B02C         /* DMA29 Current Address */
+#define DMA29_STAT                  0xFFC0B030         /* DMA29 Status Register */
+#define DMA29_XCNT_CUR              0xFFC0B034         /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA29_YCNT_CUR              0xFFC0B038         /* DMA29 Current Row Count (2D only) */
+#define DMA29_BWLCNT                0xFFC0B040         /* DMA29 Bandwidth Limit Count */
+#define DMA29_BWLCNT_CUR            0xFFC0B044         /* DMA29 Bandwidth Limit Count Current */
+#define DMA29_BWMCNT                0xFFC0B048         /* DMA29 Bandwidth Monitor Count */
+#define DMA29_BWMCNT_CUR            0xFFC0B04C         /* DMA29 Bandwidth Monitor Count Current */
+#define DMA30_DSCPTR_NXT            0xFFC0B080         /* DMA30 Pointer to Next Initial Descriptor */
+#define DMA30_ADDRSTART             0xFFC0B084         /* DMA30 Start Address of Current Buffer */
+#define DMA30_CFG                   0xFFC0B088         /* DMA30 Configuration Register */
+#define DMA30_XCNT                  0xFFC0B08C         /* DMA30 Inner Loop Count Start Value */
+#define DMA30_XMOD                  0xFFC0B090         /* DMA30 Inner Loop Address Increment */
+#define DMA30_YCNT                  0xFFC0B094         /* DMA30 Outer Loop Count Start Value (2D only) */
+#define DMA30_YMOD                  0xFFC0B098         /* DMA30 Outer Loop Address Increment (2D only) */
+#define DMA30_DSCPTR_CUR            0xFFC0B0A4         /* DMA30 Current Descriptor Pointer */
+#define DMA30_DSCPTR_PRV            0xFFC0B0A8         /* DMA30 Previous Initial Descriptor Pointer */
+#define DMA30_ADDR_CUR              0xFFC0B0AC         /* DMA30 Current Address */
+#define DMA30_STAT                  0xFFC0B0B0         /* DMA30 Status Register */
+#define DMA30_XCNT_CUR              0xFFC0B0B4         /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA30_YCNT_CUR              0xFFC0B0B8         /* DMA30 Current Row Count (2D only) */
+#define DMA30_BWLCNT                0xFFC0B0C0         /* DMA30 Bandwidth Limit Count */
+#define DMA30_BWLCNT_CUR            0xFFC0B0C4         /* DMA30 Bandwidth Limit Count Current */
+#define DMA30_BWMCNT                0xFFC0B0C8         /* DMA30 Bandwidth Monitor Count */
+#define DMA30_BWMCNT_CUR            0xFFC0B0CC         /* DMA30 Bandwidth Monitor Count Current */
+#define DMA31_DSCPTR_NXT            0xFFC0B100         /* DMA31 Pointer to Next Initial Descriptor */
+#define DMA31_ADDRSTART             0xFFC0B104         /* DMA31 Start Address of Current Buffer */
+#define DMA31_CFG                   0xFFC0B108         /* DMA31 Configuration Register */
+#define DMA31_XCNT                  0xFFC0B10C         /* DMA31 Inner Loop Count Start Value */
+#define DMA31_XMOD                  0xFFC0B110         /* DMA31 Inner Loop Address Increment */
+#define DMA31_YCNT                  0xFFC0B114         /* DMA31 Outer Loop Count Start Value (2D only) */
+#define DMA31_YMOD                  0xFFC0B118         /* DMA31 Outer Loop Address Increment (2D only) */
+#define DMA31_DSCPTR_CUR            0xFFC0B124         /* DMA31 Current Descriptor Pointer */
+#define DMA31_DSCPTR_PRV            0xFFC0B128         /* DMA31 Previous Initial Descriptor Pointer */
+#define DMA31_ADDR_CUR              0xFFC0B12C         /* DMA31 Current Address */
+#define DMA31_STAT                  0xFFC0B130         /* DMA31 Status Register */
+#define DMA31_XCNT_CUR              0xFFC0B134         /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA31_YCNT_CUR              0xFFC0B138         /* DMA31 Current Row Count (2D only) */
+#define DMA31_BWLCNT                0xFFC0B140         /* DMA31 Bandwidth Limit Count */
+#define DMA31_BWLCNT_CUR            0xFFC0B144         /* DMA31 Bandwidth Limit Count Current */
+#define DMA31_BWMCNT                0xFFC0B148         /* DMA31 Bandwidth Monitor Count */
+#define DMA31_BWMCNT_CUR            0xFFC0B14C         /* DMA31 Bandwidth Monitor Count Current */
+#define DMA32_DSCPTR_NXT            0xFFC0B180         /* DMA32 Pointer to Next Initial Descriptor */
+#define DMA32_ADDRSTART             0xFFC0B184         /* DMA32 Start Address of Current Buffer */
+#define DMA32_CFG                   0xFFC0B188         /* DMA32 Configuration Register */
+#define DMA32_XCNT                  0xFFC0B18C         /* DMA32 Inner Loop Count Start Value */
+#define DMA32_XMOD                  0xFFC0B190         /* DMA32 Inner Loop Address Increment */
+#define DMA32_YCNT                  0xFFC0B194         /* DMA32 Outer Loop Count Start Value (2D only) */
+#define DMA32_YMOD                  0xFFC0B198         /* DMA32 Outer Loop Address Increment (2D only) */
+#define DMA32_DSCPTR_CUR            0xFFC0B1A4         /* DMA32 Current Descriptor Pointer */
+#define DMA32_DSCPTR_PRV            0xFFC0B1A8         /* DMA32 Previous Initial Descriptor Pointer */
+#define DMA32_ADDR_CUR              0xFFC0B1AC         /* DMA32 Current Address */
+#define DMA32_STAT                  0xFFC0B1B0         /* DMA32 Status Register */
+#define DMA32_XCNT_CUR              0xFFC0B1B4         /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA32_YCNT_CUR              0xFFC0B1B8         /* DMA32 Current Row Count (2D only) */
+#define DMA32_BWLCNT                0xFFC0B1C0         /* DMA32 Bandwidth Limit Count */
+#define DMA32_BWLCNT_CUR            0xFFC0B1C4         /* DMA32 Bandwidth Limit Count Current */
+#define DMA32_BWMCNT                0xFFC0B1C8         /* DMA32 Bandwidth Monitor Count */
+#define DMA32_BWMCNT_CUR            0xFFC0B1CC         /* DMA32 Bandwidth Monitor Count Current */
+#define DMA33_DSCPTR_NXT            0xFFC0D000         /* DMA33 Pointer to Next Initial Descriptor */
+#define DMA33_ADDRSTART             0xFFC0D004         /* DMA33 Start Address of Current Buffer */
+#define DMA33_CFG                   0xFFC0D008         /* DMA33 Configuration Register */
+#define DMA33_XCNT                  0xFFC0D00C         /* DMA33 Inner Loop Count Start Value */
+#define DMA33_XMOD                  0xFFC0D010         /* DMA33 Inner Loop Address Increment */
+#define DMA33_YCNT                  0xFFC0D014         /* DMA33 Outer Loop Count Start Value (2D only) */
+#define DMA33_YMOD                  0xFFC0D018         /* DMA33 Outer Loop Address Increment (2D only) */
+#define DMA33_DSCPTR_CUR            0xFFC0D024         /* DMA33 Current Descriptor Pointer */
+#define DMA33_DSCPTR_PRV            0xFFC0D028         /* DMA33 Previous Initial Descriptor Pointer */
+#define DMA33_ADDR_CUR              0xFFC0D02C         /* DMA33 Current Address */
+#define DMA33_STAT                  0xFFC0D030         /* DMA33 Status Register */
+#define DMA33_XCNT_CUR              0xFFC0D034         /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA33_YCNT_CUR              0xFFC0D038         /* DMA33 Current Row Count (2D only) */
+#define DMA33_BWLCNT                0xFFC0D040         /* DMA33 Bandwidth Limit Count */
+#define DMA33_BWLCNT_CUR            0xFFC0D044         /* DMA33 Bandwidth Limit Count Current */
+#define DMA33_BWMCNT                0xFFC0D048         /* DMA33 Bandwidth Monitor Count */
+#define DMA33_BWMCNT_CUR            0xFFC0D04C         /* DMA33 Bandwidth Monitor Count Current */
+#define DMA34_DSCPTR_NXT            0xFFC0D080         /* DMA34 Pointer to Next Initial Descriptor */
+#define DMA34_ADDRSTART             0xFFC0D084         /* DMA34 Start Address of Current Buffer */
+#define DMA34_CFG                   0xFFC0D088         /* DMA34 Configuration Register */
+#define DMA34_XCNT                  0xFFC0D08C         /* DMA34 Inner Loop Count Start Value */
+#define DMA34_XMOD                  0xFFC0D090         /* DMA34 Inner Loop Address Increment */
+#define DMA34_YCNT                  0xFFC0D094         /* DMA34 Outer Loop Count Start Value (2D only) */
+#define DMA34_YMOD                  0xFFC0D098         /* DMA34 Outer Loop Address Increment (2D only) */
+#define DMA34_DSCPTR_CUR            0xFFC0D0A4         /* DMA34 Current Descriptor Pointer */
+#define DMA34_DSCPTR_PRV            0xFFC0D0A8         /* DMA34 Previous Initial Descriptor Pointer */
+#define DMA34_ADDR_CUR              0xFFC0D0AC         /* DMA34 Current Address */
+#define DMA34_STAT                  0xFFC0D0B0         /* DMA34 Status Register */
+#define DMA34_XCNT_CUR              0xFFC0D0B4         /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA34_YCNT_CUR              0xFFC0D0B8         /* DMA34 Current Row Count (2D only) */
+#define DMA34_BWLCNT                0xFFC0D0C0         /* DMA34 Bandwidth Limit Count */
+#define DMA34_BWLCNT_CUR            0xFFC0D0C4         /* DMA34 Bandwidth Limit Count Current */
+#define DMA34_BWMCNT                0xFFC0D0C8         /* DMA34 Bandwidth Monitor Count */
+#define DMA34_BWMCNT_CUR            0xFFC0D0CC         /* DMA34 Bandwidth Monitor Count Current */
+#define DMA35_DSCPTR_NXT            0xFFC10000         /* DMA35 Pointer to Next Initial Descriptor */
+#define DMA35_ADDRSTART             0xFFC10004         /* DMA35 Start Address of Current Buffer */
+#define DMA35_CFG                   0xFFC10008         /* DMA35 Configuration Register */
+#define DMA35_XCNT                  0xFFC1000C         /* DMA35 Inner Loop Count Start Value */
+#define DMA35_XMOD                  0xFFC10010         /* DMA35 Inner Loop Address Increment */
+#define DMA35_YCNT                  0xFFC10014         /* DMA35 Outer Loop Count Start Value (2D only) */
+#define DMA35_YMOD                  0xFFC10018         /* DMA35 Outer Loop Address Increment (2D only) */
+#define DMA35_DSCPTR_CUR            0xFFC10024         /* DMA35 Current Descriptor Pointer */
+#define DMA35_DSCPTR_PRV            0xFFC10028         /* DMA35 Previous Initial Descriptor Pointer */
+#define DMA35_ADDR_CUR              0xFFC1002C         /* DMA35 Current Address */
+#define DMA35_STAT                  0xFFC10030         /* DMA35 Status Register */
+#define DMA35_XCNT_CUR              0xFFC10034         /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA35_YCNT_CUR              0xFFC10038         /* DMA35 Current Row Count (2D only) */
+#define DMA35_BWLCNT                0xFFC10040         /* DMA35 Bandwidth Limit Count */
+#define DMA35_BWLCNT_CUR            0xFFC10044         /* DMA35 Bandwidth Limit Count Current */
+#define DMA35_BWMCNT                0xFFC10048         /* DMA35 Bandwidth Monitor Count */
+#define DMA35_BWMCNT_CUR            0xFFC1004C         /* DMA35 Bandwidth Monitor Count Current */
+#define DMA36_DSCPTR_NXT            0xFFC10080         /* DMA36 Pointer to Next Initial Descriptor */
+#define DMA36_ADDRSTART             0xFFC10084         /* DMA36 Start Address of Current Buffer */
+#define DMA36_CFG                   0xFFC10088         /* DMA36 Configuration Register */
+#define DMA36_XCNT                  0xFFC1008C         /* DMA36 Inner Loop Count Start Value */
+#define DMA36_XMOD                  0xFFC10090         /* DMA36 Inner Loop Address Increment */
+#define DMA36_YCNT                  0xFFC10094         /* DMA36 Outer Loop Count Start Value (2D only) */
+#define DMA36_YMOD                  0xFFC10098         /* DMA36 Outer Loop Address Increment (2D only) */
+#define DMA36_DSCPTR_CUR            0xFFC100A4         /* DMA36 Current Descriptor Pointer */
+#define DMA36_DSCPTR_PRV            0xFFC100A8         /* DMA36 Previous Initial Descriptor Pointer */
+#define DMA36_ADDR_CUR              0xFFC100AC         /* DMA36 Current Address */
+#define DMA36_STAT                  0xFFC100B0         /* DMA36 Status Register */
+#define DMA36_XCNT_CUR              0xFFC100B4         /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA36_YCNT_CUR              0xFFC100B8         /* DMA36 Current Row Count (2D only) */
+#define DMA36_BWLCNT                0xFFC100C0         /* DMA36 Bandwidth Limit Count */
+#define DMA36_BWLCNT_CUR            0xFFC100C4         /* DMA36 Bandwidth Limit Count Current */
+#define DMA36_BWMCNT                0xFFC100C8         /* DMA36 Bandwidth Monitor Count */
+#define DMA36_BWMCNT_CUR            0xFFC100CC         /* DMA36 Bandwidth Monitor Count Current */
+#define DMA37_DSCPTR_NXT            0xFFC10100         /* DMA37 Pointer to Next Initial Descriptor */
+#define DMA37_ADDRSTART             0xFFC10104         /* DMA37 Start Address of Current Buffer */
+#define DMA37_CFG                   0xFFC10108         /* DMA37 Configuration Register */
+#define DMA37_XCNT                  0xFFC1010C         /* DMA37 Inner Loop Count Start Value */
+#define DMA37_XMOD                  0xFFC10110         /* DMA37 Inner Loop Address Increment */
+#define DMA37_YCNT                  0xFFC10114         /* DMA37 Outer Loop Count Start Value (2D only) */
+#define DMA37_YMOD                  0xFFC10118         /* DMA37 Outer Loop Address Increment (2D only) */
+#define DMA37_DSCPTR_CUR            0xFFC10124         /* DMA37 Current Descriptor Pointer */
+#define DMA37_DSCPTR_PRV            0xFFC10128         /* DMA37 Previous Initial Descriptor Pointer */
+#define DMA37_ADDR_CUR              0xFFC1012C         /* DMA37 Current Address */
+#define DMA37_STAT                  0xFFC10130         /* DMA37 Status Register */
+#define DMA37_XCNT_CUR              0xFFC10134         /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA37_YCNT_CUR              0xFFC10138         /* DMA37 Current Row Count (2D only) */
+#define DMA37_BWLCNT                0xFFC10140         /* DMA37 Bandwidth Limit Count */
+#define DMA37_BWLCNT_CUR            0xFFC10144         /* DMA37 Bandwidth Limit Count Current */
+#define DMA37_BWMCNT                0xFFC10148         /* DMA37 Bandwidth Monitor Count */
+#define DMA37_BWMCNT_CUR            0xFFC1014C         /* DMA37 Bandwidth Monitor Count Current */
+#define DMA38_DSCPTR_NXT            0xFFC12000         /* DMA38 Pointer to Next Initial Descriptor */
+#define DMA38_ADDRSTART             0xFFC12004         /* DMA38 Start Address of Current Buffer */
+#define DMA38_CFG                   0xFFC12008         /* DMA38 Configuration Register */
+#define DMA38_XCNT                  0xFFC1200C         /* DMA38 Inner Loop Count Start Value */
+#define DMA38_XMOD                  0xFFC12010         /* DMA38 Inner Loop Address Increment */
+#define DMA38_YCNT                  0xFFC12014         /* DMA38 Outer Loop Count Start Value (2D only) */
+#define DMA38_YMOD                  0xFFC12018         /* DMA38 Outer Loop Address Increment (2D only) */
+#define DMA38_DSCPTR_CUR            0xFFC12024         /* DMA38 Current Descriptor Pointer */
+#define DMA38_DSCPTR_PRV            0xFFC12028         /* DMA38 Previous Initial Descriptor Pointer */
+#define DMA38_ADDR_CUR              0xFFC1202C         /* DMA38 Current Address */
+#define DMA38_STAT                  0xFFC12030         /* DMA38 Status Register */
+#define DMA38_XCNT_CUR              0xFFC12034         /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA38_YCNT_CUR              0xFFC12038         /* DMA38 Current Row Count (2D only) */
+#define DMA38_BWLCNT                0xFFC12040         /* DMA38 Bandwidth Limit Count */
+#define DMA38_BWLCNT_CUR            0xFFC12044         /* DMA38 Bandwidth Limit Count Current */
+#define DMA38_BWMCNT                0xFFC12048         /* DMA38 Bandwidth Monitor Count */
+#define DMA38_BWMCNT_CUR            0xFFC1204C         /* DMA38 Bandwidth Monitor Count Current */
+#define DMA39_DSCPTR_NXT            0xFFC12080         /* DMA39 Pointer to Next Initial Descriptor */
+#define DMA39_ADDRSTART             0xFFC12084         /* DMA39 Start Address of Current Buffer */
+#define DMA39_CFG                   0xFFC12088         /* DMA39 Configuration Register */
+#define DMA39_XCNT                  0xFFC1208C         /* DMA39 Inner Loop Count Start Value */
+#define DMA39_XMOD                  0xFFC12090         /* DMA39 Inner Loop Address Increment */
+#define DMA39_YCNT                  0xFFC12094         /* DMA39 Outer Loop Count Start Value (2D only) */
+#define DMA39_YMOD                  0xFFC12098         /* DMA39 Outer Loop Address Increment (2D only) */
+#define DMA39_DSCPTR_CUR            0xFFC120A4         /* DMA39 Current Descriptor Pointer */
+#define DMA39_DSCPTR_PRV            0xFFC120A8         /* DMA39 Previous Initial Descriptor Pointer */
+#define DMA39_ADDR_CUR              0xFFC120AC         /* DMA39 Current Address */
+#define DMA39_STAT                  0xFFC120B0         /* DMA39 Status Register */
+#define DMA39_XCNT_CUR              0xFFC120B4         /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA39_YCNT_CUR              0xFFC120B8         /* DMA39 Current Row Count (2D only) */
+#define DMA39_BWLCNT                0xFFC120C0         /* DMA39 Bandwidth Limit Count */
+#define DMA39_BWLCNT_CUR            0xFFC120C4         /* DMA39 Bandwidth Limit Count Current */
+#define DMA39_BWMCNT                0xFFC120C8         /* DMA39 Bandwidth Monitor Count */
+#define DMA39_BWMCNT_CUR            0xFFC120CC         /* DMA39 Bandwidth Monitor Count Current */
+#define DMA40_DSCPTR_NXT            0xFFC12100         /* DMA40 Pointer to Next Initial Descriptor */
+#define DMA40_ADDRSTART             0xFFC12104         /* DMA40 Start Address of Current Buffer */
+#define DMA40_CFG                   0xFFC12108         /* DMA40 Configuration Register */
+#define DMA40_XCNT                  0xFFC1210C         /* DMA40 Inner Loop Count Start Value */
+#define DMA40_XMOD                  0xFFC12110         /* DMA40 Inner Loop Address Increment */
+#define DMA40_YCNT                  0xFFC12114         /* DMA40 Outer Loop Count Start Value (2D only) */
+#define DMA40_YMOD                  0xFFC12118         /* DMA40 Outer Loop Address Increment (2D only) */
+#define DMA40_DSCPTR_CUR            0xFFC12124         /* DMA40 Current Descriptor Pointer */
+#define DMA40_DSCPTR_PRV            0xFFC12128         /* DMA40 Previous Initial Descriptor Pointer */
+#define DMA40_ADDR_CUR              0xFFC1212C         /* DMA40 Current Address */
+#define DMA40_STAT                  0xFFC12130         /* DMA40 Status Register */
+#define DMA40_XCNT_CUR              0xFFC12134         /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA40_YCNT_CUR              0xFFC12138         /* DMA40 Current Row Count (2D only) */
+#define DMA40_BWLCNT                0xFFC12140         /* DMA40 Bandwidth Limit Count */
+#define DMA40_BWLCNT_CUR            0xFFC12144         /* DMA40 Bandwidth Limit Count Current */
+#define DMA40_BWMCNT                0xFFC12148         /* DMA40 Bandwidth Monitor Count */
+#define DMA40_BWMCNT_CUR            0xFFC1214C         /* DMA40 Bandwidth Monitor Count Current */
+#define DMA41_DSCPTR_NXT            0xFFC12180         /* DMA41 Pointer to Next Initial Descriptor */
+#define DMA41_ADDRSTART             0xFFC12184         /* DMA41 Start Address of Current Buffer */
+#define DMA41_CFG                   0xFFC12188         /* DMA41 Configuration Register */
+#define DMA41_XCNT                  0xFFC1218C         /* DMA41 Inner Loop Count Start Value */
+#define DMA41_XMOD                  0xFFC12190         /* DMA41 Inner Loop Address Increment */
+#define DMA41_YCNT                  0xFFC12194         /* DMA41 Outer Loop Count Start Value (2D only) */
+#define DMA41_YMOD                  0xFFC12198         /* DMA41 Outer Loop Address Increment (2D only) */
+#define DMA41_DSCPTR_CUR            0xFFC121A4         /* DMA41 Current Descriptor Pointer */
+#define DMA41_DSCPTR_PRV            0xFFC121A8         /* DMA41 Previous Initial Descriptor Pointer */
+#define DMA41_ADDR_CUR              0xFFC121AC         /* DMA41 Current Address */
+#define DMA41_STAT                  0xFFC121B0         /* DMA41 Status Register */
+#define DMA41_XCNT_CUR              0xFFC121B4         /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA41_YCNT_CUR              0xFFC121B8         /* DMA41 Current Row Count (2D only) */
+#define DMA41_BWLCNT                0xFFC121C0         /* DMA41 Bandwidth Limit Count */
+#define DMA41_BWLCNT_CUR            0xFFC121C4         /* DMA41 Bandwidth Limit Count Current */
+#define DMA41_BWMCNT                0xFFC121C8         /* DMA41 Bandwidth Monitor Count */
+#define DMA41_BWMCNT_CUR            0xFFC121CC         /* DMA41 Bandwidth Monitor Count Current */
+#define DMA42_DSCPTR_NXT            0xFFC14000         /* DMA42 Pointer to Next Initial Descriptor */
+#define DMA42_ADDRSTART             0xFFC14004         /* DMA42 Start Address of Current Buffer */
+#define DMA42_CFG                   0xFFC14008         /* DMA42 Configuration Register */
+#define DMA42_XCNT                  0xFFC1400C         /* DMA42 Inner Loop Count Start Value */
+#define DMA42_XMOD                  0xFFC14010         /* DMA42 Inner Loop Address Increment */
+#define DMA42_YCNT                  0xFFC14014         /* DMA42 Outer Loop Count Start Value (2D only) */
+#define DMA42_YMOD                  0xFFC14018         /* DMA42 Outer Loop Address Increment (2D only) */
+#define DMA42_DSCPTR_CUR            0xFFC14024         /* DMA42 Current Descriptor Pointer */
+#define DMA42_DSCPTR_PRV            0xFFC14028         /* DMA42 Previous Initial Descriptor Pointer */
+#define DMA42_ADDR_CUR              0xFFC1402C         /* DMA42 Current Address */
+#define DMA42_STAT                  0xFFC14030         /* DMA42 Status Register */
+#define DMA42_XCNT_CUR              0xFFC14034         /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA42_YCNT_CUR              0xFFC14038         /* DMA42 Current Row Count (2D only) */
+#define DMA42_BWLCNT                0xFFC14040         /* DMA42 Bandwidth Limit Count */
+#define DMA42_BWLCNT_CUR            0xFFC14044         /* DMA42 Bandwidth Limit Count Current */
+#define DMA42_BWMCNT                0xFFC14048         /* DMA42 Bandwidth Monitor Count */
+#define DMA42_BWMCNT_CUR            0xFFC1404C         /* DMA42 Bandwidth Monitor Count Current */
+#define DMA43_DSCPTR_NXT            0xFFC14080         /* DMA43 Pointer to Next Initial Descriptor */
+#define DMA43_ADDRSTART             0xFFC14084         /* DMA43 Start Address of Current Buffer */
+#define DMA43_CFG                   0xFFC14088         /* DMA43 Configuration Register */
+#define DMA43_XCNT                  0xFFC1408C         /* DMA43 Inner Loop Count Start Value */
+#define DMA43_XMOD                  0xFFC14090         /* DMA43 Inner Loop Address Increment */
+#define DMA43_YCNT                  0xFFC14094         /* DMA43 Outer Loop Count Start Value (2D only) */
+#define DMA43_YMOD                  0xFFC14098         /* DMA43 Outer Loop Address Increment (2D only) */
+#define DMA43_DSCPTR_CUR            0xFFC140A4         /* DMA43 Current Descriptor Pointer */
+#define DMA43_DSCPTR_PRV            0xFFC140A8         /* DMA43 Previous Initial Descriptor Pointer */
+#define DMA43_ADDR_CUR              0xFFC140AC         /* DMA43 Current Address */
+#define DMA43_STAT                  0xFFC140B0         /* DMA43 Status Register */
+#define DMA43_XCNT_CUR              0xFFC140B4         /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA43_YCNT_CUR              0xFFC140B8         /* DMA43 Current Row Count (2D only) */
+#define DMA43_BWLCNT                0xFFC140C0         /* DMA43 Bandwidth Limit Count */
+#define DMA43_BWLCNT_CUR            0xFFC140C4         /* DMA43 Bandwidth Limit Count Current */
+#define DMA43_BWMCNT                0xFFC140C8         /* DMA43 Bandwidth Monitor Count */
+#define DMA43_BWMCNT_CUR            0xFFC140CC         /* DMA43 Bandwidth Monitor Count Current */
+#define DMA44_DSCPTR_NXT            0xFFC14100         /* DMA44 Pointer to Next Initial Descriptor */
+#define DMA44_ADDRSTART             0xFFC14104         /* DMA44 Start Address of Current Buffer */
+#define DMA44_CFG                   0xFFC14108         /* DMA44 Configuration Register */
+#define DMA44_XCNT                  0xFFC1410C         /* DMA44 Inner Loop Count Start Value */
+#define DMA44_XMOD                  0xFFC14110         /* DMA44 Inner Loop Address Increment */
+#define DMA44_YCNT                  0xFFC14114         /* DMA44 Outer Loop Count Start Value (2D only) */
+#define DMA44_YMOD                  0xFFC14118         /* DMA44 Outer Loop Address Increment (2D only) */
+#define DMA44_DSCPTR_CUR            0xFFC14124         /* DMA44 Current Descriptor Pointer */
+#define DMA44_DSCPTR_PRV            0xFFC14128         /* DMA44 Previous Initial Descriptor Pointer */
+#define DMA44_ADDR_CUR              0xFFC1412C         /* DMA44 Current Address */
+#define DMA44_STAT                  0xFFC14130         /* DMA44 Status Register */
+#define DMA44_XCNT_CUR              0xFFC14134         /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA44_YCNT_CUR              0xFFC14138         /* DMA44 Current Row Count (2D only) */
+#define DMA44_BWLCNT                0xFFC14140         /* DMA44 Bandwidth Limit Count */
+#define DMA44_BWLCNT_CUR            0xFFC14144         /* DMA44 Bandwidth Limit Count Current */
+#define DMA44_BWMCNT                0xFFC14148         /* DMA44 Bandwidth Monitor Count */
+#define DMA44_BWMCNT_CUR            0xFFC1414C         /* DMA44 Bandwidth Monitor Count Current */
+#define DMA45_DSCPTR_NXT            0xFFC14180         /* DMA45 Pointer to Next Initial Descriptor */
+#define DMA45_ADDRSTART             0xFFC14184         /* DMA45 Start Address of Current Buffer */
+#define DMA45_CFG                   0xFFC14188         /* DMA45 Configuration Register */
+#define DMA45_XCNT                  0xFFC1418C         /* DMA45 Inner Loop Count Start Value */
+#define DMA45_XMOD                  0xFFC14190         /* DMA45 Inner Loop Address Increment */
+#define DMA45_YCNT                  0xFFC14194         /* DMA45 Outer Loop Count Start Value (2D only) */
+#define DMA45_YMOD                  0xFFC14198         /* DMA45 Outer Loop Address Increment (2D only) */
+#define DMA45_DSCPTR_CUR            0xFFC141A4         /* DMA45 Current Descriptor Pointer */
+#define DMA45_DSCPTR_PRV            0xFFC141A8         /* DMA45 Previous Initial Descriptor Pointer */
+#define DMA45_ADDR_CUR              0xFFC141AC         /* DMA45 Current Address */
+#define DMA45_STAT                  0xFFC141B0         /* DMA45 Status Register */
+#define DMA45_XCNT_CUR              0xFFC141B4         /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA45_YCNT_CUR              0xFFC141B8         /* DMA45 Current Row Count (2D only) */
+#define DMA45_BWLCNT                0xFFC141C0         /* DMA45 Bandwidth Limit Count */
+#define DMA45_BWLCNT_CUR            0xFFC141C4         /* DMA45 Bandwidth Limit Count Current */
+#define DMA45_BWMCNT                0xFFC141C8         /* DMA45 Bandwidth Monitor Count */
+#define DMA45_BWMCNT_CUR            0xFFC141CC         /* DMA45 Bandwidth Monitor Count Current */
+#define DMA46_DSCPTR_NXT            0xFFC14200         /* DMA46 Pointer to Next Initial Descriptor */
+#define DMA46_ADDRSTART             0xFFC14204         /* DMA46 Start Address of Current Buffer */
+#define DMA46_CFG                   0xFFC14208         /* DMA46 Configuration Register */
+#define DMA46_XCNT                  0xFFC1420C         /* DMA46 Inner Loop Count Start Value */
+#define DMA46_XMOD                  0xFFC14210         /* DMA46 Inner Loop Address Increment */
+#define DMA46_YCNT                  0xFFC14214         /* DMA46 Outer Loop Count Start Value (2D only) */
+#define DMA46_YMOD                  0xFFC14218         /* DMA46 Outer Loop Address Increment (2D only) */
+#define DMA46_DSCPTR_CUR            0xFFC14224         /* DMA46 Current Descriptor Pointer */
+#define DMA46_DSCPTR_PRV            0xFFC14228         /* DMA46 Previous Initial Descriptor Pointer */
+#define DMA46_ADDR_CUR              0xFFC1422C         /* DMA46 Current Address */
+#define DMA46_STAT                  0xFFC14230         /* DMA46 Status Register */
+#define DMA46_XCNT_CUR              0xFFC14234         /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA46_YCNT_CUR              0xFFC14238         /* DMA46 Current Row Count (2D only) */
+#define DMA46_BWLCNT                0xFFC14240         /* DMA46 Bandwidth Limit Count */
+#define DMA46_BWLCNT_CUR            0xFFC14244         /* DMA46 Bandwidth Limit Count Current */
+#define DMA46_BWMCNT                0xFFC14248         /* DMA46 Bandwidth Monitor Count */
+#define DMA46_BWMCNT_CUR            0xFFC1424C         /* DMA46 Bandwidth Monitor Count Current */
+#define ACM0_CTL                    0xFFC45000         /* ACM0 ACM Control Register */
+#define ACM0_TC0                    0xFFC45004         /* ACM0 ACM Timing Configuration 0 Register */
+#define ACM0_TC1                    0xFFC45008         /* ACM0 ACM Timing Configuration 1 Register */
+#define ACM0_STAT                   0xFFC4500C         /* ACM0 ACM Status Register */
+#define ACM0_EVSTAT                 0xFFC45010         /* ACM0 ACM Event Status Register */
+#define ACM0_EVMSK                  0xFFC45014         /* ACM0 ACM Completed Event Interrupt Mask Register */
+#define ACM0_MEVSTAT                0xFFC45018         /* ACM0 ACM Missed Event Status Register */
+#define ACM0_MEVMSK                 0xFFC4501C         /* ACM0 ACM Missed Event Interrupt Mask Register */
+#define ACM0_EVCTL0                 0xFFC45020         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL1                 0xFFC45024         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL2                 0xFFC45028         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL3                 0xFFC4502C         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL4                 0xFFC45030         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL5                 0xFFC45034         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL6                 0xFFC45038         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL7                 0xFFC4503C         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL8                 0xFFC45040         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL9                 0xFFC45044         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL10                0xFFC45048         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL11                0xFFC4504C         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL12                0xFFC45050         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL13                0xFFC45054         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL14                0xFFC45058         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVCTL15                0xFFC4505C         /* ACM0 ACM Eventn Control Register */
+#define ACM0_EVTIME0                0xFFC45060         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME1                0xFFC45064         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME2                0xFFC45068         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME3                0xFFC4506C         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME4                0xFFC45070         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME5                0xFFC45074         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME6                0xFFC45078         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME7                0xFFC4507C         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME8                0xFFC45080         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME9                0xFFC45084         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME10               0xFFC45088         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME11               0xFFC4508C         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME12               0xFFC45090         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME13               0xFFC45094         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME14               0xFFC45098         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVTIME15               0xFFC4509C         /* ACM0 ACM Eventn Time Register */
+#define ACM0_EVORD0                 0xFFC450A0         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD1                 0xFFC450A4         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD2                 0xFFC450A8         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD3                 0xFFC450AC         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD4                 0xFFC450B0         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD5                 0xFFC450B4         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD6                 0xFFC450B8         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD7                 0xFFC450BC         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD8                 0xFFC450C0         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD9                 0xFFC450C4         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD10                0xFFC450C8         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD11                0xFFC450CC         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD12                0xFFC450D0         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD13                0xFFC450D4         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD14                0xFFC450D8         /* ACM0 ACM Eventn Order Register */
+#define ACM0_EVORD15                0xFFC450DC         /* ACM0 ACM Eventn Order Register */
+#define ACM0_TMR0                   0xFFC450E8         /* ACM0 ACM Timer 0 Register */
+#define ACM0_TMR1                   0xFFC450EC         /* ACM0 ACM Timer 1 Register */
+#define DMC0_ID                     0xFFC80000         /* DMC0 Identification Register */
+#define DMC0_CTL                    0xFFC80004         /* DMC0 Control Register */
+#define DMC0_STAT                   0xFFC80008         /* DMC0 Status Register */
+#define DMC0_EFFCTL                 0xFFC8000C         /* DMC0 Efficiency Controller */
+#define DMC0_PRIO                   0xFFC80010         /* DMC0 Priority ID Register */
+#define DMC0_PRIOMSK                0xFFC80014         /* DMC0 Priority ID Mask */
+#define DMC0_CFG                    0xFFC80040         /* DMC0 SDRAM Configuration */
+#define DMC0_TR0                    0xFFC80044         /* DMC0 Timing Register 0 */
+#define DMC0_TR1                    0xFFC80048         /* DMC0 Timing Register 1 */
+#define DMC0_TR2                    0xFFC8004C         /* DMC0 Timing Register 2 */
+#define DMC0_MSK                    0xFFC8005C         /* DMC0 Mode Register Mask */
+#define DMC0_MR                     0xFFC80060         /* DMC0 Mode Shadow register */
+#define DMC0_EMR1                   0xFFC80064         /* DMC0 EMR1 Shadow Register */
+#define DMC0_EMR2                   0xFFC80068         /* DMC0 EMR2 Shadow Register */
+#define DMC0_EMR3                   0xFFC8006C         /* DMC0 EMR3 Shadow Register */
+#define DMC0_DLLCTL                 0xFFC80080         /* DMC0 DLL Control Register */
+#define DMC0_PADCTL                 0xFFC800C0         /* DMC0 PAD Control Register 0 */
+#define SCB0_ARBR0                  0xFFCA2408         /* SCB0 Read-channel Arbitration Register for MIn */
+#define SCB0_ARBR1                  0xFFCA2428         /* SCB0 Read-channel Arbitration Register for MIn */
+#define SCB0_ARBR2                  0xFFCA2448         /* SCB0 Read-channel Arbitration Register for MIn */
+#define SCB0_ARBR3                  0xFFCA2468         /* SCB0 Read-channel Arbitration Register for MIn */
+#define SCB0_ARBR4                  0xFFCA2488         /* SCB0 Read-channel Arbitration Register for MIn */
+#define SCB0_ARBR5                  0xFFCA24A8         /* SCB0 Read-channel Arbitration Register for MIn */
+#define SCB0_ARBW0                  0xFFCA240C         /* SCB0 Write-channel Arbitration Register for MIn */
+#define SCB0_ARBW1                  0xFFCA242C         /* SCB0 Write-channel Arbitration Register for MIn */
+#define SCB0_ARBW2                  0xFFCA244C         /* SCB0 Write-channel Arbitration Register for MIn */
+#define SCB0_ARBW3                  0xFFCA246C         /* SCB0 Write-channel Arbitration Register for MIn */
+#define SCB0_ARBW4                  0xFFCA248C         /* SCB0 Write-channel Arbitration Register for MIn */
+#define SCB0_ARBW5                  0xFFCA24AC         /* SCB0 Write-channel Arbitration Register for MIn */
+#define SCB0_SLAVES                 0xFFCA2FC0         /* SCB0 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB0_MASTERS                0xFFCA2FC4         /* SCB0 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB1_ARBR0                  0xFFC42408         /* SCB1 Read-channel Arbitration Register for MIn */
+#define SCB1_ARBW0                  0xFFC4240C         /* SCB1 Write-channel Arbitration Register for MIn */
+#define SCB1_SLAVES                 0xFFC42FC0         /* SCB1 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB1_MASTERS                0xFFC42FC4         /* SCB1 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB2_ARBR0                  0xFFC06408         /* SCB2 Read-channel Arbitration Register for MIn */
+#define SCB2_ARBW0                  0xFFC0640C         /* SCB2 Write-channel Arbitration Register for MIn */
+#define SCB2_SLAVES                 0xFFC06FC0         /* SCB2 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB2_MASTERS                0xFFC06FC4         /* SCB2 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB3_ARBR0                  0xFFC08408         /* SCB3 Read-channel Arbitration Register for MIn */
+#define SCB3_ARBW0                  0xFFC0840C         /* SCB3 Write-channel Arbitration Register for MIn */
+#define SCB3_SLAVES                 0xFFC08FC0         /* SCB3 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB3_MASTERS                0xFFC08FC4         /* SCB3 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB4_ARBR0                  0xFFC0A408         /* SCB4 Read-channel Arbitration Register for MIn */
+#define SCB4_ARBW0                  0xFFC0A40C         /* SCB4 Write-channel Arbitration Register for MIn */
+#define SCB4_SLAVES                 0xFFC0AFC0         /* SCB4 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB4_MASTERS                0xFFC0AFC4         /* SCB4 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB5_ARBR0                  0xFFC0C408         /* SCB5 Read-channel Arbitration Register for MIn */
+#define SCB5_ARBW0                  0xFFC0C40C         /* SCB5 Write-channel Arbitration Register for MIn */
+#define SCB5_SLAVES                 0xFFC0CFC0         /* SCB5 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB5_MASTERS                0xFFC0CFC4         /* SCB5 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB6_ARBR0                  0xFFC0E408         /* SCB6 Read-channel Arbitration Register for MIn */
+#define SCB6_ARBW0                  0xFFC0E40C         /* SCB6 Write-channel Arbitration Register for MIn */
+#define SCB6_SLAVES                 0xFFC0EFC0         /* SCB6 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB6_MASTERS                0xFFC0EFC4         /* SCB6 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB7_ARBR0                  0xFFC11408         /* SCB7 Read-channel Arbitration Register for MIn */
+#define SCB7_ARBW0                  0xFFC1140C         /* SCB7 Write-channel Arbitration Register for MIn */
+#define SCB7_SLAVES                 0xFFC11FC0         /* SCB7 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB7_MASTERS                0xFFC11FC4         /* SCB7 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB8_ARBR0                  0xFFC13408         /* SCB8 Read-channel Arbitration Register for MIn */
+#define SCB8_ARBW0                  0xFFC1340C         /* SCB8 Write-channel Arbitration Register for MIn */
+#define SCB8_SLAVES                 0xFFC13FC0         /* SCB8 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB8_MASTERS                0xFFC13FC4         /* SCB8 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB9_ARBR0                  0xFFC15408         /* SCB9 Read-channel Arbitration Register for MIn */
+#define SCB9_ARBW0                  0xFFC1540C         /* SCB9 Write-channel Arbitration Register for MIn */
+#define SCB9_SLAVES                 0xFFC15FC0         /* SCB9 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB9_MASTERS                0xFFC15FC4         /* SCB9 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB10_ARBR0                 0xFFCA1408         /* SCB10 Read-channel Arbitration Register for MIn */
+#define SCB10_ARBR1                 0xFFCA1428         /* SCB10 Read-channel Arbitration Register for MIn */
+#define SCB10_ARBR2                 0xFFCA1448         /* SCB10 Read-channel Arbitration Register for MIn */
+#define SCB10_ARBW0                 0xFFCA140C         /* SCB10 Write-channel Arbitration Register for MIn */
+#define SCB10_ARBW1                 0xFFCA142C         /* SCB10 Write-channel Arbitration Register for MIn */
+#define SCB10_ARBW2                 0xFFCA144C         /* SCB10 Write-channel Arbitration Register for MIn */
+#define SCB10_SLAVES                0xFFCA1FC0         /* SCB10 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB10_MASTERS               0xFFCA1FC4         /* SCB10 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define SCB11_ARBR0                 0xFFCA0408         /* SCB11 Read-channel Arbitration Register for MIn */
+#define SCB11_ARBR1                 0xFFCA0428         /* SCB11 Read-channel Arbitration Register for MIn */
+#define SCB11_ARBR2                 0xFFCA0448         /* SCB11 Read-channel Arbitration Register for MIn */
+#define SCB11_ARBR3                 0xFFCA0468         /* SCB11 Read-channel Arbitration Register for MIn */
+#define SCB11_ARBR4                 0xFFCA0488         /* SCB11 Read-channel Arbitration Register for MIn */
+#define SCB11_ARBR5                 0xFFCA04A8         /* SCB11 Read-channel Arbitration Register for MIn */
+#define SCB11_ARBR6                 0xFFCA04C8         /* SCB11 Read-channel Arbitration Register for MIn */
+#define SCB11_ARBW0                 0xFFCA040C         /* SCB11 Write-channel Arbitration Register for MIn */
+#define SCB11_ARBW1                 0xFFCA042C         /* SCB11 Write-channel Arbitration Register for MIn */
+#define SCB11_ARBW2                 0xFFCA044C         /* SCB11 Write-channel Arbitration Register for MIn */
+#define SCB11_ARBW3                 0xFFCA046C         /* SCB11 Write-channel Arbitration Register for MIn */
+#define SCB11_ARBW4                 0xFFCA048C         /* SCB11 Write-channel Arbitration Register for MIn */
+#define SCB11_ARBW5                 0xFFCA04AC         /* SCB11 Write-channel Arbitration Register for MIn */
+#define SCB11_ARBW6                 0xFFCA04CC         /* SCB11 Write-channel Arbitration Register for MIn */
+#define SCB11_SLAVES                0xFFCA0FC0         /* SCB11 Number of Slave Interfaces in Matrix (Reset = $NUM_SLOTS) */
+#define SCB11_MASTERS               0xFFCA0FC4         /* SCB11 Number of Master Interfaces in Matrix (Reset = $NUM_MASTERS) */
+#define L2_CTL                      0xFFCA3000         /* L2CTL0 L2 Control Register */
+#define L2_ACTL_C0                  0xFFCA3004         /* L2CTL0 L2 Core 0 Access Control Register */
+#define L2_ACTL_C1                  0xFFCA3008         /* L2CTL0 L2 Core 1 Access Control Register */
+#define L2_ACTL_SYS                 0xFFCA300C         /* L2CTL0 L2 System Access Control Register */
+#define L2_STAT                 0xFFCA3010         /* L2CTL0 L2 Status Register */
+#define L2_RPCR                 0xFFCA3014         /* L2CTL0 L2 Read Priority Count Register */
+#define L2_WPCR                 0xFFCA3018         /* L2CTL0 L2 Write Priority Count Register */
+#define L2_RFA                  0xFFCA3024         /* L2CTL0 L2 Refresh Address Regsiter */
+#define L2_ERRADDR0             0xFFCA3040         /* L2CTL0 L2 Bank 0 ECC Error Address Register */
+#define L2_ERRADDR1             0xFFCA3044         /* L2CTL0 L2 Bank 1 ECC Error Address Register */
+#define L2_ERRADDR2             0xFFCA3048         /* L2CTL0 L2 Bank 2 ECC Error Address Register */
+#define L2_ERRADDR3             0xFFCA304C         /* L2CTL0 L2 Bank 3 ECC Error Address Register */
+#define L2_ERRADDR4             0xFFCA3050         /* L2CTL0 L2 Bank 4 ECC Error Address Register */
+#define L2_ERRADDR5             0xFFCA3054         /* L2CTL0 L2 Bank 5 ECC Error Address Register */
+#define L2_ERRADDR6             0xFFCA3058         /* L2CTL0 L2 Bank 6 ECC Error Address Register */
+#define L2_ERRADDR7             0xFFCA305C         /* L2CTL0 L2 Bank 7 ECC Error Address Register */
+#define L2_ET0                  0xFFCA3080         /* L2CTL0 L2 AXI Error 0 Type Register */
+#define L2_EADDR0               0xFFCA3084         /* L2CTL0 L2 AXI Error 0 Address Register */
+#define L2_ET1                  0xFFCA3088         /* L2CTL0 L2 AXI Error 1 Type Register */
+#define L2_EADDR1               0xFFCA308C         /* L2CTL0 L2 AXI Error 1 Address Register */
+#define SEC0_CCTL0                  0xFFCA4400         /* SEC0 Core Control Register n */
+#define SEC0_CCTL1                  0xFFCA4440         /* SEC0 Core Control Register n */
+#define SEC0_CSTAT0                 0xFFCA4404         /* SEC0 Core Status Register n */
+#define SEC0_CSTAT1                 0xFFCA4444         /* SEC0 Core Status Register n */
+#define SEC0_CPND0                  0xFFCA4408         /* SEC0 Core Pending IRQ Register n */
+#define SEC0_CPND1                  0xFFCA4448         /* SEC0 Core Pending IRQ Register n */
+#define SEC0_CACT0                  0xFFCA440C         /* SEC0 Core Active IRQ Register n */
+#define SEC0_CACT1                  0xFFCA444C         /* SEC0 Core Active IRQ Register n */
+#define SEC0_CPMSK0                 0xFFCA4410         /* SEC0 Core IRQ Priority Mask Register n */
+#define SEC0_CPMSK1                 0xFFCA4450         /* SEC0 Core IRQ Priority Mask Register n */
+#define SEC0_CGMSK0                 0xFFCA4414         /* SEC0 Core IRQ Group Mask Register n */
+#define SEC0_CGMSK1                 0xFFCA4454         /* SEC0 Core IRQ Group Mask Register n */
+#define SEC0_CPLVL0                 0xFFCA4418         /* SEC0 Core IRQ Priority Level Register n */
+#define SEC0_CPLVL1                 0xFFCA4458         /* SEC0 Core IRQ Priority Level Register n */
+#define SEC0_CSID0                  0xFFCA441C         /* SEC0 Core IRQ Source ID Register n */
+#define SEC0_CSID1                  0xFFCA445C         /* SEC0 Core IRQ Source ID Register n */
+#define SEC0_FCTL                   0xFFCA4010         /* SEC0 Fault Control Register */
+#define SEC0_FSTAT                  0xFFCA4014         /* SEC0 Fault Status Register */
+#define SEC0_FSID                   0xFFCA4018         /* SEC0 Fault Source ID Register */
+#define SEC0_FEND                   0xFFCA401C         /* SEC0 Fault End Register */
+#define SEC0_FDLY                   0xFFCA4020         /* SEC0 Fault Delay Register */
+#define SEC0_FDLY_CUR               0xFFCA4024         /* SEC0 Fault Delay Current Register */
+#define SEC0_FSRDLY                 0xFFCA4028         /* SEC0 Fault System Reset Delay Register */
+#define SEC0_FSRDLY_CUR             0xFFCA402C         /* SEC0 Fault System Reset Delay Current Register */
+#define SEC0_FCOPP                  0xFFCA4030         /* SEC0 Fault COP Period Register */
+#define SEC0_FCOPP_CUR              0xFFCA4034         /* SEC0 Fault COP Period Current Register */
+#define SEC0_GCTL                   0xFFCA4000         /* SEC0 Global Control Register */
+#define SEC0_GSTAT                  0xFFCA4004         /* SEC0 Global Status Register */
+#define SEC0_RAISE                  0xFFCA4008         /* SEC0 Global Raise Register */
+#define SEC0_END                    0xFFCA400C         /* SEC0 Global End Register */
+#define SEC0_SCTL0                  0xFFCA4800         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL1                  0xFFCA4808         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL2                  0xFFCA4810         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL3                  0xFFCA4818         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL4                  0xFFCA4820         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL5                  0xFFCA4828         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL6                  0xFFCA4830         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL7                  0xFFCA4838         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL8                  0xFFCA4840         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL9                  0xFFCA4848         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL10                 0xFFCA4850         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL11                 0xFFCA4858         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL12                 0xFFCA4860         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL13                 0xFFCA4868         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL14                 0xFFCA4870         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL15                 0xFFCA4878         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL16                 0xFFCA4880         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL17                 0xFFCA4888         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL18                 0xFFCA4890         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL19                 0xFFCA4898         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL20                 0xFFCA48A0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL21                 0xFFCA48A8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL22                 0xFFCA48B0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL23                 0xFFCA48B8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL24                 0xFFCA48C0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL25                 0xFFCA48C8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL26                 0xFFCA48D0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL27                 0xFFCA48D8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL28                 0xFFCA48E0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL29                 0xFFCA48E8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL30                 0xFFCA48F0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL31                 0xFFCA48F8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL32                 0xFFCA4900         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL33                 0xFFCA4908         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL34                 0xFFCA4910         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL35                 0xFFCA4918         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL36                 0xFFCA4920         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL37                 0xFFCA4928         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL38                 0xFFCA4930         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL39                 0xFFCA4938         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL40                 0xFFCA4940         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL41                 0xFFCA4948         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL42                 0xFFCA4950         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL43                 0xFFCA4958         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL44                 0xFFCA4960         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL45                 0xFFCA4968         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL46                 0xFFCA4970         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL47                 0xFFCA4978         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL48                 0xFFCA4980         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL49                 0xFFCA4988         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL50                 0xFFCA4990         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL51                 0xFFCA4998         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL52                 0xFFCA49A0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL53                 0xFFCA49A8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL54                 0xFFCA49B0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL55                 0xFFCA49B8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL56                 0xFFCA49C0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL57                 0xFFCA49C8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL58                 0xFFCA49D0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL59                 0xFFCA49D8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL60                 0xFFCA49E0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL61                 0xFFCA49E8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL62                 0xFFCA49F0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL63                 0xFFCA49F8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL64                 0xFFCA4A00         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL65                 0xFFCA4A08         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL66                 0xFFCA4A10         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL67                 0xFFCA4A18         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL68                 0xFFCA4A20         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL69                 0xFFCA4A28         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL70                 0xFFCA4A30         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL71                 0xFFCA4A38         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL72                 0xFFCA4A40         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL73                 0xFFCA4A48         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL74                 0xFFCA4A50         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL75                 0xFFCA4A58         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL76                 0xFFCA4A60         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL77                 0xFFCA4A68         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL78                 0xFFCA4A70         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL79                 0xFFCA4A78         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL80                 0xFFCA4A80         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL81                 0xFFCA4A88         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL82                 0xFFCA4A90         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL83                 0xFFCA4A98         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL84                 0xFFCA4AA0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL85                 0xFFCA4AA8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL86                 0xFFCA4AB0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL87                 0xFFCA4AB8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL88                 0xFFCA4AC0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL89                 0xFFCA4AC8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL90                 0xFFCA4AD0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL91                 0xFFCA4AD8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL92                 0xFFCA4AE0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL93                 0xFFCA4AE8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL94                 0xFFCA4AF0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL95                 0xFFCA4AF8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL96                 0xFFCA4B00         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL97                 0xFFCA4B08         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL98                 0xFFCA4B10         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL99                 0xFFCA4B18         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL100                0xFFCA4B20         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL101                0xFFCA4B28         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL102                0xFFCA4B30         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL103                0xFFCA4B38         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL104                0xFFCA4B40         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL105                0xFFCA4B48         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL106                0xFFCA4B50         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL107                0xFFCA4B58         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL108                0xFFCA4B60         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL109                0xFFCA4B68         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL110                0xFFCA4B70         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL111                0xFFCA4B78         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL112                0xFFCA4B80         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL113                0xFFCA4B88         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL114                0xFFCA4B90         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL115                0xFFCA4B98         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL116                0xFFCA4BA0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL117                0xFFCA4BA8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL118                0xFFCA4BB0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL119                0xFFCA4BB8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL120                0xFFCA4BC0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL121                0xFFCA4BC8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL122                0xFFCA4BD0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL123                0xFFCA4BD8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL124                0xFFCA4BE0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL125                0xFFCA4BE8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL126                0xFFCA4BF0         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL127                0xFFCA4BF8         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL128                0xFFCA4C00         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL129                0xFFCA4C08         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL130                0xFFCA4C10         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL131                0xFFCA4C18         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL132                0xFFCA4C20         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL133                0xFFCA4C28         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL134                0xFFCA4C30         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL135                0xFFCA4C38         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL136                0xFFCA4C40         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL137                0xFFCA4C48         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL138                0xFFCA4C50         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SCTL139                0xFFCA4C58         /* SEC0 IRQ Source Control Register n */
+#define SEC0_SSTAT0                 0xFFCA4804         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT1                 0xFFCA480C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT2                 0xFFCA4814         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT3                 0xFFCA481C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT4                 0xFFCA4824         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT5                 0xFFCA482C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT6                 0xFFCA4834         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT7                 0xFFCA483C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT8                 0xFFCA4844         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT9                 0xFFCA484C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT10                0xFFCA4854         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT11                0xFFCA485C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT12                0xFFCA4864         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT13                0xFFCA486C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT14                0xFFCA4874         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT15                0xFFCA487C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT16                0xFFCA4884         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT17                0xFFCA488C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT18                0xFFCA4894         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT19                0xFFCA489C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT20                0xFFCA48A4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT21                0xFFCA48AC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT22                0xFFCA48B4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT23                0xFFCA48BC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT24                0xFFCA48C4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT25                0xFFCA48CC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT26                0xFFCA48D4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT27                0xFFCA48DC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT28                0xFFCA48E4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT29                0xFFCA48EC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT30                0xFFCA48F4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT31                0xFFCA48FC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT32                0xFFCA4904         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT33                0xFFCA490C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT34                0xFFCA4914         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT35                0xFFCA491C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT36                0xFFCA4924         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT37                0xFFCA492C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT38                0xFFCA4934         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT39                0xFFCA493C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT40                0xFFCA4944         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT41                0xFFCA494C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT42                0xFFCA4954         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT43                0xFFCA495C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT44                0xFFCA4964         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT45                0xFFCA496C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT46                0xFFCA4974         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT47                0xFFCA497C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT48                0xFFCA4984         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT49                0xFFCA498C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT50                0xFFCA4994         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT51                0xFFCA499C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT52                0xFFCA49A4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT53                0xFFCA49AC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT54                0xFFCA49B4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT55                0xFFCA49BC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT56                0xFFCA49C4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT57                0xFFCA49CC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT58                0xFFCA49D4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT59                0xFFCA49DC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT60                0xFFCA49E4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT61                0xFFCA49EC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT62                0xFFCA49F4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT63                0xFFCA49FC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT64                0xFFCA4A04         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT65                0xFFCA4A0C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT66                0xFFCA4A14         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT67                0xFFCA4A1C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT68                0xFFCA4A24         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT69                0xFFCA4A2C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT70                0xFFCA4A34         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT71                0xFFCA4A3C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT72                0xFFCA4A44         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT73                0xFFCA4A4C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT74                0xFFCA4A54         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT75                0xFFCA4A5C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT76                0xFFCA4A64         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT77                0xFFCA4A6C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT78                0xFFCA4A74         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT79                0xFFCA4A7C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT80                0xFFCA4A84         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT81                0xFFCA4A8C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT82                0xFFCA4A94         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT83                0xFFCA4A9C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT84                0xFFCA4AA4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT85                0xFFCA4AAC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT86                0xFFCA4AB4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT87                0xFFCA4ABC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT88                0xFFCA4AC4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT89                0xFFCA4ACC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT90                0xFFCA4AD4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT91                0xFFCA4ADC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT92                0xFFCA4AE4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT93                0xFFCA4AEC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT94                0xFFCA4AF4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT95                0xFFCA4AFC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT96                0xFFCA4B04         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT97                0xFFCA4B0C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT98                0xFFCA4B14         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT99                0xFFCA4B1C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT100               0xFFCA4B24         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT101               0xFFCA4B2C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT102               0xFFCA4B34         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT103               0xFFCA4B3C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT104               0xFFCA4B44         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT105               0xFFCA4B4C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT106               0xFFCA4B54         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT107               0xFFCA4B5C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT108               0xFFCA4B64         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT109               0xFFCA4B6C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT110               0xFFCA4B74         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT111               0xFFCA4B7C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT112               0xFFCA4B84         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT113               0xFFCA4B8C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT114               0xFFCA4B94         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT115               0xFFCA4B9C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT116               0xFFCA4BA4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT117               0xFFCA4BAC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT118               0xFFCA4BB4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT119               0xFFCA4BBC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT120               0xFFCA4BC4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT121               0xFFCA4BCC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT122               0xFFCA4BD4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT123               0xFFCA4BDC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT124               0xFFCA4BE4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT125               0xFFCA4BEC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT126               0xFFCA4BF4         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT127               0xFFCA4BFC         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT128               0xFFCA4C04         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT129               0xFFCA4C0C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT130               0xFFCA4C14         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT131               0xFFCA4C1C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT132               0xFFCA4C24         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT133               0xFFCA4C2C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT134               0xFFCA4C34         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT135               0xFFCA4C3C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT136               0xFFCA4C44         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT137               0xFFCA4C4C         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT138               0xFFCA4C54         /* SEC0 IRQ Source Status Register n */
+#define SEC0_SSTAT139               0xFFCA4C5C         /* SEC0 IRQ Source Status Register n */
+#define TRU0_SSR0                   0xFFCA5000         /* TRU0 Slave Select Register */
+#define TRU0_SSR1                   0xFFCA5004         /* TRU0 Slave Select Register */
+#define TRU0_SSR2                   0xFFCA5008         /* TRU0 Slave Select Register */
+#define TRU0_SSR3                   0xFFCA500C         /* TRU0 Slave Select Register */
+#define TRU0_SSR4                   0xFFCA5010         /* TRU0 Slave Select Register */
+#define TRU0_SSR5                   0xFFCA5014         /* TRU0 Slave Select Register */
+#define TRU0_SSR6                   0xFFCA5018         /* TRU0 Slave Select Register */
+#define TRU0_SSR7                   0xFFCA501C         /* TRU0 Slave Select Register */
+#define TRU0_SSR8                   0xFFCA5020         /* TRU0 Slave Select Register */
+#define TRU0_SSR9                   0xFFCA5024         /* TRU0 Slave Select Register */
+#define TRU0_SSR10                  0xFFCA5028         /* TRU0 Slave Select Register */
+#define TRU0_SSR11                  0xFFCA502C         /* TRU0 Slave Select Register */
+#define TRU0_SSR12                  0xFFCA5030         /* TRU0 Slave Select Register */
+#define TRU0_SSR13                  0xFFCA5034         /* TRU0 Slave Select Register */
+#define TRU0_SSR14                  0xFFCA5038         /* TRU0 Slave Select Register */
+#define TRU0_SSR15                  0xFFCA503C         /* TRU0 Slave Select Register */
+#define TRU0_SSR16                  0xFFCA5040         /* TRU0 Slave Select Register */
+#define TRU0_SSR17                  0xFFCA5044         /* TRU0 Slave Select Register */
+#define TRU0_SSR18                  0xFFCA5048         /* TRU0 Slave Select Register */
+#define TRU0_SSR19                  0xFFCA504C         /* TRU0 Slave Select Register */
+#define TRU0_SSR20                  0xFFCA5050         /* TRU0 Slave Select Register */
+#define TRU0_SSR21                  0xFFCA5054         /* TRU0 Slave Select Register */
+#define TRU0_SSR22                  0xFFCA5058         /* TRU0 Slave Select Register */
+#define TRU0_SSR23                  0xFFCA505C         /* TRU0 Slave Select Register */
+#define TRU0_SSR24                  0xFFCA5060         /* TRU0 Slave Select Register */
+#define TRU0_SSR25                  0xFFCA5064         /* TRU0 Slave Select Register */
+#define TRU0_SSR26                  0xFFCA5068         /* TRU0 Slave Select Register */
+#define TRU0_SSR27                  0xFFCA506C         /* TRU0 Slave Select Register */
+#define TRU0_SSR28                  0xFFCA5070         /* TRU0 Slave Select Register */
+#define TRU0_SSR29                  0xFFCA5074         /* TRU0 Slave Select Register */
+#define TRU0_SSR30                  0xFFCA5078         /* TRU0 Slave Select Register */
+#define TRU0_SSR31                  0xFFCA507C         /* TRU0 Slave Select Register */
+#define TRU0_SSR32                  0xFFCA5080         /* TRU0 Slave Select Register */
+#define TRU0_SSR33                  0xFFCA5084         /* TRU0 Slave Select Register */
+#define TRU0_SSR34                  0xFFCA5088         /* TRU0 Slave Select Register */
+#define TRU0_SSR35                  0xFFCA508C         /* TRU0 Slave Select Register */
+#define TRU0_SSR36                  0xFFCA5090         /* TRU0 Slave Select Register */
+#define TRU0_SSR37                  0xFFCA5094         /* TRU0 Slave Select Register */
+#define TRU0_SSR38                  0xFFCA5098         /* TRU0 Slave Select Register */
+#define TRU0_SSR39                  0xFFCA509C         /* TRU0 Slave Select Register */
+#define TRU0_SSR40                  0xFFCA50A0         /* TRU0 Slave Select Register */
+#define TRU0_SSR41                  0xFFCA50A4         /* TRU0 Slave Select Register */
+#define TRU0_SSR42                  0xFFCA50A8         /* TRU0 Slave Select Register */
+#define TRU0_SSR43                  0xFFCA50AC         /* TRU0 Slave Select Register */
+#define TRU0_SSR44                  0xFFCA50B0         /* TRU0 Slave Select Register */
+#define TRU0_SSR45                  0xFFCA50B4         /* TRU0 Slave Select Register */
+#define TRU0_SSR46                  0xFFCA50B8         /* TRU0 Slave Select Register */
+#define TRU0_SSR47                  0xFFCA50BC         /* TRU0 Slave Select Register */
+#define TRU0_SSR48                  0xFFCA50C0         /* TRU0 Slave Select Register */
+#define TRU0_SSR49                  0xFFCA50C4         /* TRU0 Slave Select Register */
+#define TRU0_SSR50                  0xFFCA50C8         /* TRU0 Slave Select Register */
+#define TRU0_SSR51                  0xFFCA50CC         /* TRU0 Slave Select Register */
+#define TRU0_SSR52                  0xFFCA50D0         /* TRU0 Slave Select Register */
+#define TRU0_SSR53                  0xFFCA50D4         /* TRU0 Slave Select Register */
+#define TRU0_SSR54                  0xFFCA50D8         /* TRU0 Slave Select Register */
+#define TRU0_SSR55                  0xFFCA50DC         /* TRU0 Slave Select Register */
+#define TRU0_SSR56                  0xFFCA50E0         /* TRU0 Slave Select Register */
+#define TRU0_SSR57                  0xFFCA50E4         /* TRU0 Slave Select Register */
+#define TRU0_SSR58                  0xFFCA50E8         /* TRU0 Slave Select Register */
+#define TRU0_SSR59                  0xFFCA50EC         /* TRU0 Slave Select Register */
+#define TRU0_SSR60                  0xFFCA50F0         /* TRU0 Slave Select Register */
+#define TRU0_SSR61                  0xFFCA50F4         /* TRU0 Slave Select Register */
+#define TRU0_SSR62                  0xFFCA50F8         /* TRU0 Slave Select Register */
+#define TRU0_SSR63                  0xFFCA50FC         /* TRU0 Slave Select Register */
+#define TRU0_SSR64                  0xFFCA5100         /* TRU0 Slave Select Register */
+#define TRU0_SSR65                  0xFFCA5104         /* TRU0 Slave Select Register */
+#define TRU0_SSR66                  0xFFCA5108         /* TRU0 Slave Select Register */
+#define TRU0_SSR67                  0xFFCA510C         /* TRU0 Slave Select Register */
+#define TRU0_SSR68                  0xFFCA5110         /* TRU0 Slave Select Register */
+#define TRU0_SSR69                  0xFFCA5114         /* TRU0 Slave Select Register */
+#define TRU0_SSR70                  0xFFCA5118         /* TRU0 Slave Select Register */
+#define TRU0_SSR71                  0xFFCA511C         /* TRU0 Slave Select Register */
+#define TRU0_SSR72                  0xFFCA5120         /* TRU0 Slave Select Register */
+#define TRU0_SSR73                  0xFFCA5124         /* TRU0 Slave Select Register */
+#define TRU0_SSR74                  0xFFCA5128         /* TRU0 Slave Select Register */
+#define TRU0_SSR75                  0xFFCA512C         /* TRU0 Slave Select Register */
+#define TRU0_SSR76                  0xFFCA5130         /* TRU0 Slave Select Register */
+#define TRU0_SSR77                  0xFFCA5134         /* TRU0 Slave Select Register */
+#define TRU0_SSR78                  0xFFCA5138         /* TRU0 Slave Select Register */
+#define TRU0_SSR79                  0xFFCA513C         /* TRU0 Slave Select Register */
+#define TRU0_SSR80                  0xFFCA5140         /* TRU0 Slave Select Register */
+#define TRU0_SSR81                  0xFFCA5144         /* TRU0 Slave Select Register */
+#define TRU0_SSR82                  0xFFCA5148         /* TRU0 Slave Select Register */
+#define TRU0_SSR83                  0xFFCA514C         /* TRU0 Slave Select Register */
+#define TRU0_SSR84                  0xFFCA5150         /* TRU0 Slave Select Register */
+#define TRU0_SSR85                  0xFFCA5154         /* TRU0 Slave Select Register */
+#define TRU0_SSR86                  0xFFCA5158         /* TRU0 Slave Select Register */
+#define TRU0_MTR                    0xFFCA57E0         /* TRU0 Master Trigger Register */
+#define TRU0_ERRADDR                0xFFCA57E8         /* TRU0 Error Address Register */
+#define TRU0_STAT                   0xFFCA57EC         /* TRU0 Status Information Register */
+#define TRU0_REVID                  0xFFCA57F0         /* TRU0 Revision ID Register */
+#define TRU0_GCTL                   0xFFCA57F4         /* TRU0 Global Control Register */
+#define RCU0_CTL                    0xFFCA6000         /* RCU0 Control Register */
+#define RCU0_STAT                   0xFFCA6004         /* RCU0 Status Register */
+#define RCU0_CRCTL                  0xFFCA6008         /* RCU0 Core Reset Control Register */
+#define RCU0_CRSTAT                 0xFFCA600C         /* RCU0 Core Reset Status Register */
+#define RCU0_SIDIS                  0xFFCA6010         /* RCU0 System Interface Disable Register */
+#define RCU0_SISTAT                 0xFFCA6014         /* RCU0 System Interface Status Register */
+#define RCU0_SVECT_LCK              0xFFCA6018         /* RCU0 SVECT Lock Register */
+#define RCU0_BCODE                  0xFFCA601C         /* RCU0 Boot Code Register */
+#define RCU0_SVECT0                 0xFFCA6020         /* RCU0 Software Vector Register n */
+#define RCU0_SVECT1                 0xFFCA6024         /* RCU0 Software Vector Register n */
+#define SPU0_CTL                    0xFFCA7000         /* SPU0 Control Register */
+#define SPU0_STAT                   0xFFCA7004         /* SPU0 Status Register */
+#define SPU0_WP0                    0xFFCA7400         /* SPU0 Write Protect Register n */
+#define SPU0_WP1                    0xFFCA7404         /* SPU0 Write Protect Register n */
+#define SPU0_WP2                    0xFFCA7408         /* SPU0 Write Protect Register n */
+#define SPU0_WP3                    0xFFCA740C         /* SPU0 Write Protect Register n */
+#define SPU0_WP4                    0xFFCA7410         /* SPU0 Write Protect Register n */
+#define SPU0_WP5                    0xFFCA7414         /* SPU0 Write Protect Register n */
+#define SPU0_WP6                    0xFFCA7418         /* SPU0 Write Protect Register n */
+#define SPU0_WP7                    0xFFCA741C         /* SPU0 Write Protect Register n */
+#define SPU0_WP8                    0xFFCA7420         /* SPU0 Write Protect Register n */
+#define SPU0_WP9                    0xFFCA7424         /* SPU0 Write Protect Register n */
+#define SPU0_WP10                   0xFFCA7428         /* SPU0 Write Protect Register n */
+#define SPU0_WP11                   0xFFCA742C         /* SPU0 Write Protect Register n */
+#define SPU0_WP12                   0xFFCA7430         /* SPU0 Write Protect Register n */
+#define SPU0_WP13                   0xFFCA7434         /* SPU0 Write Protect Register n */
+#define SPU0_WP14                   0xFFCA7438         /* SPU0 Write Protect Register n */
+#define SPU0_WP15                   0xFFCA743C         /* SPU0 Write Protect Register n */
+#define SPU0_WP16                   0xFFCA7440         /* SPU0 Write Protect Register n */
+#define SPU0_WP17                   0xFFCA7444         /* SPU0 Write Protect Register n */
+#define SPU0_WP18                   0xFFCA7448         /* SPU0 Write Protect Register n */
+#define SPU0_WP19                   0xFFCA744C         /* SPU0 Write Protect Register n */
+#define SPU0_WP20                   0xFFCA7450         /* SPU0 Write Protect Register n */
+#define SPU0_WP21                   0xFFCA7454         /* SPU0 Write Protect Register n */
+#define SPU0_WP22                   0xFFCA7458         /* SPU0 Write Protect Register n */
+#define SPU0_WP23                   0xFFCA745C         /* SPU0 Write Protect Register n */
+#define SPU0_WP24                   0xFFCA7460         /* SPU0 Write Protect Register n */
+#define SPU0_WP25                   0xFFCA7464         /* SPU0 Write Protect Register n */
+#define SPU0_WP26                   0xFFCA7468         /* SPU0 Write Protect Register n */
+#define SPU0_WP27                   0xFFCA746C         /* SPU0 Write Protect Register n */
+#define SPU0_WP28                   0xFFCA7470         /* SPU0 Write Protect Register n */
+#define SPU0_WP29                   0xFFCA7474         /* SPU0 Write Protect Register n */
+#define SPU0_WP30                   0xFFCA7478         /* SPU0 Write Protect Register n */
+#define SPU0_WP31                   0xFFCA747C         /* SPU0 Write Protect Register n */
+#define SPU0_WP32                   0xFFCA7480         /* SPU0 Write Protect Register n */
+#define SPU0_WP33                   0xFFCA7484         /* SPU0 Write Protect Register n */
+#define SPU0_WP34                   0xFFCA7488         /* SPU0 Write Protect Register n */
+#define SPU0_WP35                   0xFFCA748C         /* SPU0 Write Protect Register n */
+#define SPU0_WP36                   0xFFCA7490         /* SPU0 Write Protect Register n */
+#define SPU0_WP37                   0xFFCA7494         /* SPU0 Write Protect Register n */
+#define SPU0_WP38                   0xFFCA7498         /* SPU0 Write Protect Register n */
+#define SPU0_WP39                   0xFFCA749C         /* SPU0 Write Protect Register n */
+#define SPU0_WP40                   0xFFCA74A0         /* SPU0 Write Protect Register n */
+#define SPU0_WP41                   0xFFCA74A4         /* SPU0 Write Protect Register n */
+#define SPU0_WP42                   0xFFCA74A8         /* SPU0 Write Protect Register n */
+#define SPU0_WP43                   0xFFCA74AC         /* SPU0 Write Protect Register n */
+#define SPU0_WP44                   0xFFCA74B0         /* SPU0 Write Protect Register n */
+#define SPU0_WP45                   0xFFCA74B4         /* SPU0 Write Protect Register n */
+#define SPU0_WP46                   0xFFCA74B8         /* SPU0 Write Protect Register n */
+#define SPU0_WP47                   0xFFCA74BC         /* SPU0 Write Protect Register n */
+#define SPU0_WP48                   0xFFCA74C0         /* SPU0 Write Protect Register n */
+#define SPU0_WP49                   0xFFCA74C4         /* SPU0 Write Protect Register n */
+#define SPU0_WP50                   0xFFCA74C8         /* SPU0 Write Protect Register n */
+#define SPU0_WP51                   0xFFCA74CC         /* SPU0 Write Protect Register n */
+#define SPU0_WP52                   0xFFCA74D0         /* SPU0 Write Protect Register n */
+#define SPU0_WP53                   0xFFCA74D4         /* SPU0 Write Protect Register n */
+#define SPU0_WP54                   0xFFCA74D8         /* SPU0 Write Protect Register n */
+#define SPU0_WP55                   0xFFCA74DC         /* SPU0 Write Protect Register n */
+#define SPU0_WP56                   0xFFCA74E0         /* SPU0 Write Protect Register n */
+#define SPU0_WP57                   0xFFCA74E4         /* SPU0 Write Protect Register n */
+#define SPU0_WP58                   0xFFCA74E8         /* SPU0 Write Protect Register n */
+#define SPU0_WP59                   0xFFCA74EC         /* SPU0 Write Protect Register n */
+#define SPU0_WP60                   0xFFCA74F0         /* SPU0 Write Protect Register n */
+#define SPU0_WP61                   0xFFCA74F4         /* SPU0 Write Protect Register n */
+#define SPU0_WP62                   0xFFCA74F8         /* SPU0 Write Protect Register n */
+#define SPU0_WP63                   0xFFCA74FC         /* SPU0 Write Protect Register n */
+#define SPU0_WP64                   0xFFCA7500         /* SPU0 Write Protect Register n */
+#define SPU0_WP65                   0xFFCA7504         /* SPU0 Write Protect Register n */
+#define SPU0_WP66                   0xFFCA7508         /* SPU0 Write Protect Register n */
+#define SPU0_WP67                   0xFFCA750C         /* SPU0 Write Protect Register n */
+#define SPU0_WP68                   0xFFCA7510         /* SPU0 Write Protect Register n */
+#define SPU0_WP69                   0xFFCA7514         /* SPU0 Write Protect Register n */
+#define SPU0_WP70                   0xFFCA7518         /* SPU0 Write Protect Register n */
+#define SPU0_WP71                   0xFFCA751C         /* SPU0 Write Protect Register n */
+#define SPU0_WP72                   0xFFCA7520         /* SPU0 Write Protect Register n */
+#define SPU0_WP73                   0xFFCA7524         /* SPU0 Write Protect Register n */
+#define SPU0_WP74                   0xFFCA7528         /* SPU0 Write Protect Register n */
+#define SPU0_WP75                   0xFFCA752C         /* SPU0 Write Protect Register n */
+#define SPU0_WP76                   0xFFCA7530         /* SPU0 Write Protect Register n */
+#define SPU0_WP77                   0xFFCA7534         /* SPU0 Write Protect Register n */
+#define SPU0_WP78                   0xFFCA7538         /* SPU0 Write Protect Register n */
+#define SPU0_WP79                   0xFFCA753C         /* SPU0 Write Protect Register n */
+#define SPU0_WP80                   0xFFCA7540         /* SPU0 Write Protect Register n */
+#define SPU0_WP81                   0xFFCA7544         /* SPU0 Write Protect Register n */
+#define SPU0_WP82                   0xFFCA7548         /* SPU0 Write Protect Register n */
+#define SPU0_WP83                   0xFFCA754C         /* SPU0 Write Protect Register n */
+#define SPU0_WP84                   0xFFCA7550         /* SPU0 Write Protect Register n */
+#define SPU0_WP85                   0xFFCA7554         /* SPU0 Write Protect Register n */
+#define CGU_CTL                    0xFFCA8000         /* CGU0 Control Register */
+#define CGU_STAT                   0xFFCA8004         /* CGU0 Status Register */
+#define CGU_DIV                    0xFFCA8008         /* CGU0 Divisor Register */
+#define CGU_CLKOUTSEL              0xFFCA800C         /* CGU0 CLKOUT Select Register */
+#define DPM0_CTL                    0xFFCA9000         /* DPM0 Control Register */
+#define DPM0_STAT                   0xFFCA9004         /* DPM0 Status Register */
+#define DPM0_CCBF_DIS               0xFFCA9008         /* DPM0 Core Clock Buffer Disable Register */
+#define DPM0_CCBF_EN                0xFFCA900C         /* DPM0 Core Clock Buffer Enable Register */
+#define DPM0_CCBF_STAT              0xFFCA9010         /* DPM0 Core Clock Buffer Status Register */
+#define DPM0_CCBF_STAT_STKY         0xFFCA9014         /* DPM0 Core Clock Buffer Status Sticky Register */
+#define DPM0_SCBF_DIS               0xFFCA9018         /* DPM0 System Clock Buffer Disable Register */
+#define DPM0_WAKE_EN                0xFFCA901C         /* DPM0 Wakeup Enable Register */
+#define DPM0_WAKE_POL               0xFFCA9020         /* DPM0 Wakeup Polarity Register */
+#define DPM0_WAKE_STAT              0xFFCA9024         /* DPM0 Wakeup Status Register */
+#define DPM0_HIB_DIS                0xFFCA9028         /* DPM0 Hibernate Disable Register */
+#define DPM0_PGCNTR                 0xFFCA902C         /* DPM0 Power Good Counter Register */
+#define DPM0_RESTORE0               0xFFCA9030         /* DPM0 Restore Register */
+#define DPM0_RESTORE1               0xFFCA9034         /* DPM0 Restore Register */
+#define DPM0_RESTORE2               0xFFCA9038         /* DPM0 Restore Register */
+#define DPM0_RESTORE3               0xFFCA903C         /* DPM0 Restore Register */
+#define DPM0_RESTORE4               0xFFCA9040         /* DPM0 Restore Register */
+#define DPM0_RESTORE5               0xFFCA9044         /* DPM0 Restore Register */
+#define DPM0_RESTORE6               0xFFCA9048         /* DPM0 Restore Register */
+#define DPM0_RESTORE7               0xFFCA904C         /* DPM0 Restore Register */
+#define DPM0_RESTORE8               0xFFCA9050         /* DPM0 Restore Register */
+#define DPM0_RESTORE9               0xFFCA9054         /* DPM0 Restore Register */
+#define DPM0_RESTORE10              0xFFCA9058         /* DPM0 Restore Register */
+#define DPM0_RESTORE11              0xFFCA905C         /* DPM0 Restore Register */
+#define DPM0_RESTORE12              0xFFCA9060         /* DPM0 Restore Register */
+#define DPM0_RESTORE13              0xFFCA9064         /* DPM0 Restore Register */
+#define DPM0_RESTORE14              0xFFCA9068         /* DPM0 Restore Register */
+#define DPM0_RESTORE15              0xFFCA906C         /* DPM0 Restore Register */
+#define EFS0_CTL                    0xFFCC0000         /* EFS0 Control Register */
+#define EFS0_DAT0                   0xFFCC0008         /* EFS0 Data Register 0 */
+#define EFS0_DAT1                   0xFFCC000C         /* EFS0 Data Register 1 */
+#define EFS0_DAT2                   0xFFCC0010         /* EFS0 Data Register 2 */
+#define EFS0_DAT3                   0xFFCC0014         /* EFS0 Data Register 3 */
+#define EFS0_DAT4                   0xFFCC0018         /* EFS0 Data Register 4 */
+#define EFS0_DAT5                   0xFFCC001C         /* EFS0 Data Register 5 */
+#define EFS0_DAT6                   0xFFCC0020         /* EFS0 Data Register 6 */
+#define EFS0_DAT7                   0xFFCC0024         /* EFS0 Data Register 7 */
+#define EFS0_PGM0                   0xFFCC0028         /* EFS0 Program Register 0 */
+#define EFS0_PGM1                   0xFFCC002C         /* EFS0 Program Register 1 */
+#define EFS0_PGM2                   0xFFCC0030         /* EFS0 Program Register 2 */
+#define EFS0_PGM3                   0xFFCC0034         /* EFS0 Program Register 3 */
+#define EFS0_PGM4                   0xFFCC0038         /* EFS0 Program Register 4 */
+#define EFS0_PGM5                   0xFFCC003C         /* EFS0 Program Register 5 */
+#define EFS0_PGM6                   0xFFCC0040         /* EFS0 Program Register 6 */
+#define EFS0_PGM7                   0xFFCC0044         /* EFS0 Program Register 7 */
+#define EFS0_PGM_TIMING             0xFFCC007C         /* EFS0 Timing configuration register */
+#define USB_FADDR                  0xFFCC1000         /* USB Device Address in Peripheral Mode */
+#define USB_POWER                  0xFFCC1001         /* USB Power and Device Control */
+#define USB_INTRTX                 0xFFCC1002         /* USB Transmit Interrupt */
+#define USB_INTRRX                 0xFFCC1004         /* USB Receive Interrupts */
+#define USB_INTRTXE                0xFFCC1006         /* USB Transmit Interrupt Enable */
+#define USB_INTRRXE                0xFFCC1008         /* USB Receive Interrupt Enable */
+#define USB_IRQ                    0xFFCC100A         /* USB USB Interrupts */
+#define USB_IEN                    0xFFCC100B         /* USB USB Interrupt Enable */
+#define USB_FRAME                  0xFFCC100C         /* USB Frame Number */
+#define USB_INDEX                  0xFFCC100E         /* USB Index */
+#define USB_TESTMODE               0xFFCC100F         /* USB Testmodes */
+#define USB_EPI_TXMAXP0            0xFFCC1010         /* USB Transmit Maximum Packet Length */
+#define USB_EP0I_CSR0_H            0xFFCC1012         /* USB Config and Status EP0 */
+#define USB_EPI_TXCSR0_H           0xFFCC1012         /* USB Transmit Configuration and Status */
+#define USB_EP0I_CSR0_P            0xFFCC1012         /* USB Config and Status EP0 */
+#define USB_EPI_TXCSR0_P           0xFFCC1012         /* USB Transmit Configuration and Status */
+#define USB_EPI_RXMAXP0            0xFFCC1014         /* USB Receive Maximum Packet Length */
+#define USB_EPI_RXCSR0_H           0xFFCC1016         /* USB Receive Configuration and Status Register */
+#define USB_EPI_RXCSR0_P           0xFFCC1016         /* USB Receive Configuration and Status Register */
+#define USB_EP0I_CNT0              0xFFCC1018         /* USB Number of Received Bytes for Endpoint 0 */
+#define USB_EPI_RXCNT0             0xFFCC1018         /* USB Number of Byte Received */
+#define USB_EP0I_TYPE0             0xFFCC101A         /* USB Speed for Endpoint 0 */
+#define USB_EPI_TXTYPE0            0xFFCC101A         /* USB Transmit Type */
+#define USB_EP0I_NAKLIMIT0         0xFFCC101B         /* USB NAK Response Timeout for Endpoint 0 */
+#define USB_EPI_TXINTERVAL0        0xFFCC101B         /* USB Transmit Polling Interval */
+#define USB_EPI_RXTYPE0            0xFFCC101C         /* USB Receive Type */
+#define USB_EPI_RXINTERVAL0        0xFFCC101D         /* USB Receive Polling Interval */
+#define USB_EP0I_CFGDATA0          0xFFCC101F         /* USB Configuration Information */
+#define USB_FIFOB0                 0xFFCC1020         /* USB FIFO Data */
+#define USB_FIFOB1                 0xFFCC1024         /* USB FIFO Data */
+#define USB_FIFOB2                 0xFFCC1028         /* USB FIFO Data */
+#define USB_FIFOB3                 0xFFCC102C         /* USB FIFO Data */
+#define USB_FIFOB4                 0xFFCC1030         /* USB FIFO Data */
+#define USB_FIFOB5                 0xFFCC1034         /* USB FIFO Data */
+#define USB_FIFOB6                 0xFFCC1038         /* USB FIFO Data */
+#define USB_FIFOB7                 0xFFCC103C         /* USB FIFO Data */
+#define USB_FIFOB8                 0xFFCC1040         /* USB FIFO Data */
+#define USB_FIFOB9                 0xFFCC1044         /* USB FIFO Data */
+#define USB_FIFOB10                0xFFCC1048         /* USB FIFO Data */
+#define USB_FIFOB11                0xFFCC104C         /* USB FIFO Data */
+#define USB_FIFOH0                 0xFFCC1020         /* USB FIFO Data */
+#define USB_FIFOH1                 0xFFCC1024         /* USB FIFO Data */
+#define USB_FIFOH2                 0xFFCC1028         /* USB FIFO Data */
+#define USB_FIFOH3                 0xFFCC102C         /* USB FIFO Data */
+#define USB_FIFOH4                 0xFFCC1030         /* USB FIFO Data */
+#define USB_FIFOH5                 0xFFCC1034         /* USB FIFO Data */
+#define USB_FIFOH6                 0xFFCC1038         /* USB FIFO Data */
+#define USB_FIFOH7                 0xFFCC103C         /* USB FIFO Data */
+#define USB_FIFOH8                 0xFFCC1040         /* USB FIFO Data */
+#define USB_FIFOH9                 0xFFCC1044         /* USB FIFO Data */
+#define USB_FIFOH10                0xFFCC1048         /* USB FIFO Data */
+#define USB_FIFOH11                0xFFCC104C         /* USB FIFO Data */
+#define USB_FIFO0                  0xFFCC1020         /* USB FIFO Data */
+#define USB_FIFO1                  0xFFCC1024         /* USB FIFO Data */
+#define USB_FIFO2                  0xFFCC1028         /* USB FIFO Data */
+#define USB_FIFO3                  0xFFCC102C         /* USB FIFO Data */
+#define USB_FIFO4                  0xFFCC1030         /* USB FIFO Data */
+#define USB_FIFO5                  0xFFCC1034         /* USB FIFO Data */
+#define USB_FIFO6                  0xFFCC1038         /* USB FIFO Data */
+#define USB_FIFO7                  0xFFCC103C         /* USB FIFO Data */
+#define USB_FIFO8                  0xFFCC1040         /* USB FIFO Data */
+#define USB_FIFO9                  0xFFCC1044         /* USB FIFO Data */
+#define USB_FIFO10                 0xFFCC1048         /* USB FIFO Data */
+#define USB_FIFO11                 0xFFCC104C         /* USB FIFO Data */
+#define USB_DEV_CTL                0xFFCC1060         /* USB Device Control */
+#define USB_TXFIFOSZ               0xFFCC1062         /* USB Transmit FIFO Size */
+#define USB_RXFIFOSZ               0xFFCC1063         /* USB Receive FIFO Size */
+#define USB_TXFIFOADDR             0xFFCC1064         /* USB Transmit FIFO Address */
+#define USB_RXFIFOADDR             0xFFCC1066         /* USB Receive FIFO Address */
+#define USB_VENDSTAT               0xFFCC1068         /* USB Vendor Status */
+#define USB_HWVERS                 0xFFCC106C         /* USB Hardware Version */
+#define USB_EPINFO                 0xFFCC1078         /* USB Endpoint Info */
+#define USB_RAMINFO                0xFFCC1079         /* USB Ram Information */
+#define USB_LINKINFO               0xFFCC107A         /* USB Programmable Delay Values */
+#define USB_VPLEN                  0xFFCC107B         /* USB VBus Pulse Duration */
+#define USB_HS_EOF1                0xFFCC107C         /* USB High Speed End of Frame Remaining */
+#define USB_FS_EOF1                0xFFCC107D         /* USB Full Speed End of Frame Remaining */
+#define USB_LS_EOF1                0xFFCC107E         /* USB Low Speed End of Frame Remaining */
+#define USB_SOFT_RST               0xFFCC107F         /* USB Software Reset */
+#define USB_TXFUNCADDR0            0xFFCC1080         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR1            0xFFCC1088         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR2            0xFFCC1090         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR3            0xFFCC1098         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR4            0xFFCC10A0         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR5            0xFFCC10A8         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR6            0xFFCC10B0         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR7            0xFFCC10B8         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR8            0xFFCC10C0         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR9            0xFFCC10C8         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR10           0xFFCC10D0         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR11           0xFFCC10D8         /* USB Transmit Function Address */
+#define USB_TXHUBADDR0             0xFFCC1082         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR1             0xFFCC108A         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR2             0xFFCC1092         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR3             0xFFCC109A         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR4             0xFFCC10A2         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR5             0xFFCC10AA         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR6             0xFFCC10B2         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR7             0xFFCC10BA         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR8             0xFFCC10C2         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR9             0xFFCC10CA         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR10            0xFFCC10D2         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR11            0xFFCC10DA         /* USB Transmit Hub Address */
+#define USB_TXHUBPORT0             0xFFCC1083         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT1             0xFFCC108B         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT2             0xFFCC1093         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT3             0xFFCC109B         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT4             0xFFCC10A3         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT5             0xFFCC10AB         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT6             0xFFCC10B3         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT7             0xFFCC10BB         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT8             0xFFCC10C3         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT9             0xFFCC10CB         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT10            0xFFCC10D3         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT11            0xFFCC10DB         /* USB Transmit Hub Port */
+#define USB_RXFUNCADDR0            0xFFCC1084         /* USB Receive Function Address */
+#define USB_RXFUNCADDR1            0xFFCC108C         /* USB Receive Function Address */
+#define USB_RXFUNCADDR2            0xFFCC1094         /* USB Receive Function Address */
+#define USB_RXFUNCADDR3            0xFFCC109C         /* USB Receive Function Address */
+#define USB_RXFUNCADDR4            0xFFCC10A4         /* USB Receive Function Address */
+#define USB_RXFUNCADDR5            0xFFCC10AC         /* USB Receive Function Address */
+#define USB_RXFUNCADDR6            0xFFCC10B4         /* USB Receive Function Address */
+#define USB_RXFUNCADDR7            0xFFCC10BC         /* USB Receive Function Address */
+#define USB_RXFUNCADDR8            0xFFCC10C4         /* USB Receive Function Address */
+#define USB_RXFUNCADDR9            0xFFCC10CC         /* USB Receive Function Address */
+#define USB_RXFUNCADDR10           0xFFCC10D4         /* USB Receive Function Address */
+#define USB_RXFUNCADDR11           0xFFCC10DC         /* USB Receive Function Address */
+#define USB_RXHUBADDR0             0xFFCC1086         /* USB Receive Hub Address */
+#define USB_RXHUBADDR1             0xFFCC108E         /* USB Receive Hub Address */
+#define USB_RXHUBADDR2             0xFFCC1096         /* USB Receive Hub Address */
+#define USB_RXHUBADDR3             0xFFCC109E         /* USB Receive Hub Address */
+#define USB_RXHUBADDR4             0xFFCC10A6         /* USB Receive Hub Address */
+#define USB_RXHUBADDR5             0xFFCC10AE         /* USB Receive Hub Address */
+#define USB_RXHUBADDR6             0xFFCC10B6         /* USB Receive Hub Address */
+#define USB_RXHUBADDR7             0xFFCC10BE         /* USB Receive Hub Address */
+#define USB_RXHUBADDR8             0xFFCC10C6         /* USB Receive Hub Address */
+#define USB_RXHUBADDR9             0xFFCC10CE         /* USB Receive Hub Address */
+#define USB_RXHUBADDR10            0xFFCC10D6         /* USB Receive Hub Address */
+#define USB_RXHUBADDR11            0xFFCC10DE         /* USB Receive Hub Address */
+#define USB_RXHUBPORT0             0xFFCC1087         /* USB Receive Hub Port */
+#define USB_RXHUBPORT1             0xFFCC108F         /* USB Receive Hub Port */
+#define USB_RXHUBPORT2             0xFFCC1097         /* USB Receive Hub Port */
+#define USB_RXHUBPORT3             0xFFCC109F         /* USB Receive Hub Port */
+#define USB_RXHUBPORT4             0xFFCC10A7         /* USB Receive Hub Port */
+#define USB_RXHUBPORT5             0xFFCC10AF         /* USB Receive Hub Port */
+#define USB_RXHUBPORT6             0xFFCC10B7         /* USB Receive Hub Port */
+#define USB_RXHUBPORT7             0xFFCC10BF         /* USB Receive Hub Port */
+#define USB_RXHUBPORT8             0xFFCC10C7         /* USB Receive Hub Port */
+#define USB_RXHUBPORT9             0xFFCC10CF         /* USB Receive Hub Port */
+#define USB_RXHUBPORT10            0xFFCC10D7         /* USB Receive Hub Port */
+#define USB_RXHUBPORT11            0xFFCC10DF         /* USB Receive Hub Port */
+#define USB_EP0_CSR0_H             0xFFCC1102         /* USB Config and Status EP0 */
+#define USB_EP0_CSR0_P             0xFFCC1102         /* USB Config and Status EP0 */
+#define USB_EP0_CNT0               0xFFCC1108         /* USB Number of Received Bytes for Endpoint 0 */
+#define USB_EP0_TYPE0              0xFFCC110A         /* USB Speed for Endpoint 0 */
+#define USB_EP0_NAKLIMIT0          0xFFCC110B         /* USB NAK Response Timeout for Endpoint 0 */
+#define USB_EP0_CFGDATA0           0xFFCC110F         /* USB Configuration Information */
+#define USB_EP_TXMAXP0             0xFFCC1110         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP1             0xFFCC1120         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP2             0xFFCC1130         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP3             0xFFCC1140         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP4             0xFFCC1150         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP5             0xFFCC1160         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP6             0xFFCC1170         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP7             0xFFCC1180         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP8             0xFFCC1190         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP9             0xFFCC11A0         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP10            0xFFCC11B0         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXCSR0_H            0xFFCC1112         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR1_H            0xFFCC1122         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR2_H            0xFFCC1132         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR3_H            0xFFCC1142         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR4_H            0xFFCC1152         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR5_H            0xFFCC1162         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR6_H            0xFFCC1172         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR7_H            0xFFCC1182         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR8_H            0xFFCC1192         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR9_H            0xFFCC11A2         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR10_H           0xFFCC11B2         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR0_P            0xFFCC1112         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR1_P            0xFFCC1122         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR2_P            0xFFCC1132         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR3_P            0xFFCC1142         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR4_P            0xFFCC1152         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR5_P            0xFFCC1162         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR6_P            0xFFCC1172         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR7_P            0xFFCC1182         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR8_P            0xFFCC1192         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR9_P            0xFFCC11A2         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR10_P           0xFFCC11B2         /* USB Transmit Configuration and Status */
+#define USB_EP_RXMAXP0             0xFFCC1114         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP1             0xFFCC1124         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP2             0xFFCC1134         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP3             0xFFCC1144         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP4             0xFFCC1154         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP5             0xFFCC1164         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP6             0xFFCC1174         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP7             0xFFCC1184         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP8             0xFFCC1194         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP9             0xFFCC11A4         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP10            0xFFCC11B4         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXCSR0_H            0xFFCC1116         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR1_H            0xFFCC1126         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR2_H            0xFFCC1136         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR3_H            0xFFCC1146         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR4_H            0xFFCC1156         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR5_H            0xFFCC1166         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR6_H            0xFFCC1176         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR7_H            0xFFCC1186         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR8_H            0xFFCC1196         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR9_H            0xFFCC11A6         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR10_H           0xFFCC11B6         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR0_P            0xFFCC1116         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR1_P            0xFFCC1126         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR2_P            0xFFCC1136         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR3_P            0xFFCC1146         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR4_P            0xFFCC1156         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR5_P            0xFFCC1166         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR6_P            0xFFCC1176         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR7_P            0xFFCC1186         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR8_P            0xFFCC1196         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR9_P            0xFFCC11A6         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR10_P           0xFFCC11B6         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCNT0              0xFFCC1118         /* USB Number of Byte Received */
+#define USB_EP_RXCNT1              0xFFCC1128         /* USB Number of Byte Received */
+#define USB_EP_RXCNT2              0xFFCC1138         /* USB Number of Byte Received */
+#define USB_EP_RXCNT3              0xFFCC1148         /* USB Number of Byte Received */
+#define USB_EP_RXCNT4              0xFFCC1158         /* USB Number of Byte Received */
+#define USB_EP_RXCNT5              0xFFCC1168         /* USB Number of Byte Received */
+#define USB_EP_RXCNT6              0xFFCC1178         /* USB Number of Byte Received */
+#define USB_EP_RXCNT7              0xFFCC1188         /* USB Number of Byte Received */
+#define USB_EP_RXCNT8              0xFFCC1198         /* USB Number of Byte Received */
+#define USB_EP_RXCNT9              0xFFCC11A8         /* USB Number of Byte Received */
+#define USB_EP_RXCNT10             0xFFCC11B8         /* USB Number of Byte Received */
+#define USB_EP_TXTYPE0             0xFFCC111A         /* USB Transmit Type */
+#define USB_EP_TXTYPE1             0xFFCC112A         /* USB Transmit Type */
+#define USB_EP_TXTYPE2             0xFFCC113A         /* USB Transmit Type */
+#define USB_EP_TXTYPE3             0xFFCC114A         /* USB Transmit Type */
+#define USB_EP_TXTYPE4             0xFFCC115A         /* USB Transmit Type */
+#define USB_EP_TXTYPE5             0xFFCC116A         /* USB Transmit Type */
+#define USB_EP_TXTYPE6             0xFFCC117A         /* USB Transmit Type */
+#define USB_EP_TXTYPE7             0xFFCC118A         /* USB Transmit Type */
+#define USB_EP_TXTYPE8             0xFFCC119A         /* USB Transmit Type */
+#define USB_EP_TXTYPE9             0xFFCC11AA         /* USB Transmit Type */
+#define USB_EP_TXTYPE10            0xFFCC11BA         /* USB Transmit Type */
+#define USB_EP_TXINTERVAL0         0xFFCC111B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL1         0xFFCC112B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL2         0xFFCC113B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL3         0xFFCC114B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL4         0xFFCC115B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL5         0xFFCC116B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL6         0xFFCC117B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL7         0xFFCC118B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL8         0xFFCC119B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL9         0xFFCC11AB         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL10        0xFFCC11BB         /* USB Transmit Polling Interval */
+#define USB_EP_RXTYPE0             0xFFCC111C         /* USB Receive Type */
+#define USB_EP_RXTYPE1             0xFFCC112C         /* USB Receive Type */
+#define USB_EP_RXTYPE2             0xFFCC113C         /* USB Receive Type */
+#define USB_EP_RXTYPE3             0xFFCC114C         /* USB Receive Type */
+#define USB_EP_RXTYPE4             0xFFCC115C         /* USB Receive Type */
+#define USB_EP_RXTYPE5             0xFFCC116C         /* USB Receive Type */
+#define USB_EP_RXTYPE6             0xFFCC117C         /* USB Receive Type */
+#define USB_EP_RXTYPE7             0xFFCC118C         /* USB Receive Type */
+#define USB_EP_RXTYPE8             0xFFCC119C         /* USB Receive Type */
+#define USB_EP_RXTYPE9             0xFFCC11AC         /* USB Receive Type */
+#define USB_EP_RXTYPE10            0xFFCC11BC         /* USB Receive Type */
+#define USB_EP_RXINTERVAL0         0xFFCC111D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL1         0xFFCC112D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL2         0xFFCC113D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL3         0xFFCC114D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL4         0xFFCC115D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL5         0xFFCC116D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL6         0xFFCC117D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL7         0xFFCC118D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL8         0xFFCC119D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL9         0xFFCC11AD         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL10        0xFFCC11BD         /* USB Receive Polling Interval */
+#define USB_DMA_IRQ                0xFFCC1200         /* USB Interrupt Register */
+#define USB_DMA_CTL0               0xFFCC1204         /* USB DMA Control */
+#define USB_DMA_CTL1               0xFFCC1214         /* USB DMA Control */
+#define USB_DMA_CTL2               0xFFCC1224         /* USB DMA Control */
+#define USB_DMA_CTL3               0xFFCC1234         /* USB DMA Control */
+#define USB_DMA_CTL4               0xFFCC1244         /* USB DMA Control */
+#define USB_DMA_CTL5               0xFFCC1254         /* USB DMA Control */
+#define USB_DMA_CTL6               0xFFCC1264         /* USB DMA Control */
+#define USB_DMA_CTL7               0xFFCC1274         /* USB DMA Control */
+#define USB_DMA_ADDR0              0xFFCC1208         /* USB DMA Address */
+#define USB_DMA_ADDR1              0xFFCC1218         /* USB DMA Address */
+#define USB_DMA_ADDR2              0xFFCC1228         /* USB DMA Address */
+#define USB_DMA_ADDR3              0xFFCC1238         /* USB DMA Address */
+#define USB_DMA_ADDR4              0xFFCC1248         /* USB DMA Address */
+#define USB_DMA_ADDR5              0xFFCC1258         /* USB DMA Address */
+#define USB_DMA_ADDR6              0xFFCC1268         /* USB DMA Address */
+#define USB_DMA_ADDR7              0xFFCC1278         /* USB DMA Address */
+#define USB_DMA_CNT0               0xFFCC120C         /* USB DMA Count */
+#define USB_DMA_CNT1               0xFFCC121C         /* USB DMA Count */
+#define USB_DMA_CNT2               0xFFCC122C         /* USB DMA Count */
+#define USB_DMA_CNT3               0xFFCC123C         /* USB DMA Count */
+#define USB_DMA_CNT4               0xFFCC124C         /* USB DMA Count */
+#define USB_DMA_CNT5               0xFFCC125C         /* USB DMA Count */
+#define USB_DMA_CNT6               0xFFCC126C         /* USB DMA Count */
+#define USB_DMA_CNT7               0xFFCC127C         /* USB DMA Count */
+#define USB_RQPKTCNT0              0xFFCC1300         /* USB Request Packet Count */
+#define USB_RQPKTCNT1              0xFFCC1304         /* USB Request Packet Count */
+#define USB_RQPKTCNT2              0xFFCC1308         /* USB Request Packet Count */
+#define USB_RQPKTCNT3              0xFFCC130C         /* USB Request Packet Count */
+#define USB_RQPKTCNT4              0xFFCC1310         /* USB Request Packet Count */
+#define USB_RQPKTCNT5              0xFFCC1314         /* USB Request Packet Count */
+#define USB_RQPKTCNT6              0xFFCC1318         /* USB Request Packet Count */
+#define USB_RQPKTCNT7              0xFFCC131C         /* USB Request Packet Count */
+#define USB_RQPKTCNT8              0xFFCC1320         /* USB Request Packet Count */
+#define USB_RQPKTCNT9              0xFFCC1324         /* USB Request Packet Count */
+#define USB_RQPKTCNT10             0xFFCC1328         /* USB Request Packet Count */
+#define USB_CT_UCH                 0xFFCC1344         /* USB Chirp Timeout */
+#define USB_CT_HHSRTN              0xFFCC1346         /* USB High Speed Resume Return to Normal */
+#define USB_CT_HSBT                0xFFCC1348         /* USB High Speed Timeout */
+#define USB_LPM_ATTR               0xFFCC1360         /* USB LPM Attribute */
+#define USB_LPM_CTL                0xFFCC1362         /* USB LPM Control */
+#define USB_LPM_IEN                0xFFCC1363         /* USB LPM Interrupt Enable */
+#define USB_LPM_IRQ                0xFFCC1364         /* USB LPM Interrupt */
+#define USB_LPM_FADDR              0xFFCC1365         /* USB LPM Function Address */
+#define USB_VBUS_CTL               0xFFCC1380         /* USB VBus Control */
+#define USB_BAT_CHG                0xFFCC1381         /* USB Battery Charging */
+#define USB_PHY_CTL                0xFFCC1394         /* USB PHY Control */
+#define USB_TESTCTL                0xFFCC1397         /* USB Test Control */
+#define USB_PLL_OSC                0xFFCC1398         /* USB PLL and Oscillator Control */
+
+#define                           CHIPID  0xffc00014
+/* CHIPID Masks */
+#define                   CHIPID_VERSION  0xF0000000
+#define                    CHIPID_FAMILY  0x0FFFF000
+#define               CHIPID_MANUFACTURE  0x00000FFE
+
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE 0x8000
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE 0x4000
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE 0x8000
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF609_proc__ */
diff --git a/arch/blackfin/include/asm/mach-bf609/anomaly.h b/arch/blackfin/include/asm/mach-bf609/anomaly.h
new file mode 100644
index 0000000..b52e0c3
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/anomaly.h
@@ -0,0 +1,103 @@ 
+/*
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
+ *
+ * Copyright 2004-2012 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
+ */
+
+/* This file should be up to date with:
+ *  - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
+ */
+
+#if __SILICON_REVISION__ < 0
+# error will not work on BF609 silicon version
+#endif
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
+#define ANOMALY_16000003 (1)
+/* The EPPI Data Enable (DEN) Signal is Not Functional */
+#define ANOMALY_16000004 (1)
+/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
+#define ANOMALY_16000005 (1)
+/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
+#define ANOMALY_16000006 (1)
+/* DDR2 Memory Reads May Fail Intermittently */
+#define ANOMALY_16000007 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
+#define ANOMALY_16000008 (1)
+/* TestSET Instruction Cannot Be Interrupted */
+#define ANOMALY_16000009 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_16000010 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_16000011 (1)
+/* Speculative Fetches of Indirect-Pointer Inst Can Cause False Hw Errors */
+#define ANOMALY_16000012 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_16000013 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_16000014 (1)
+/* Multi-Issue Inst with dsp32shiftimm in slot1 and P in slot2 Not Supported */
+#define ANOMALY_16000015 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_16000017 (1)
+/* RSI Boot Cleanup Routine Does Not Clear Registers */
+#define ANOMALY_16000018 (1)
+/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
+#define ANOMALY_16000019 (1)
+/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
+#define ANOMALY_16000020 (1)
+/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hb/Wk Sequence */
+#define ANOMALY_16000021 (1)
+/* Boot Code Fails to Enable Parity Fault Detection */
+#define ANOMALY_16000022 (1)
+/* USB DMA interrupt status do not show the DMA channel intr in the DMA ISR */
+#define ANOMALY_16000027 (1)
+/* Interrupted Core Reads of MMRs May Cause Data Loss */
+#define ANOMALY_16000030 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000189 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000219 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000274 (0)
+#define ANOMALY_05000278 (0)
+#define ANOMALY_05000281 (0)
+#define ANOMALY_05000287 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000386 (0)
+#define ANOMALY_05000480 (0)
+#define ANOMALY_05000481 (1)
+
+/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
+#define ANOMALY_05000491 ANOMALY_16000008
+#define ANOMALY_05000477 ANOMALY_16000009
+#define ANOMALY_05000443 ANOMALY_16000010
+#define ANOMALY_05000461 ANOMALY_16000011
+#define ANOMALY_05000426 ANOMALY_16000012
+#define ANOMALY_05000310 ANOMALY_16000013
+#define ANOMALY_05000245 ANOMALY_16000014
+#define ANOMALY_05000074 ANOMALY_16000015
+#define ANOMALY_05000416 ANOMALY_16000017
+
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-bf609/def_local.h b/arch/blackfin/include/asm/mach-bf609/def_local.h
new file mode 100644
index 0000000..d4250e6
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/def_local.h
@@ -0,0 +1,5 @@ 
+#include "gpio.h"
+#include "portmux.h"
+#include "ports.h"
+
+#define CONFIG_BF60x 1	/* Linux glue */
diff --git a/arch/blackfin/include/asm/mach-bf609/portmux.h b/arch/blackfin/include/asm/mach-bf609/portmux.h
new file mode 100644
index 0000000..757570f
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/portmux.h
@@ -0,0 +1,257 @@ 
+/*
+ * Copyright 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
+
+/* EMAC RMII Port Mux */
+#define P_MII0_MDC	(P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
+#define P_MII0_MDIO	(P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
+#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
+#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
+#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
+#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
+#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
+#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
+#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
+#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
+#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
+
+#define P_RMII0 {\
+	P_MII0_ETxD0, \
+	P_MII0_ETxD1, \
+	P_MII0_ETxEN, \
+	P_MII0_ERxD0, \
+	P_MII0_ERxD1, \
+	P_MII0_ERxER, \
+	P_MII0_TxCLK, \
+	P_MII0_PHYINT, \
+	P_MII0_CRS, \
+	P_MII0_MDC, \
+	P_PTP0_PPS, \
+	P_PTP1_PPS, \
+	P_MII0_MDIO, 0}
+
+#define P_MII1_MDC	(P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
+#define P_MII1_MDIO	(P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
+#define P_MII1_ETxD0	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_MII1_ERxD0	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#define P_MII1_ETxD1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+#define P_MII1_ERxD1	(P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
+#define P_MII1_ETxEN	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_MII1_PHYINT	(P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
+#define P_MII1_CRS	(P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
+#define P_MII1_ERxER	(P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
+#define P_MII1_TxCLK	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+
+#define P_RMII1 {\
+	P_MII1_ETxD0, \
+	P_MII1_ETxD1, \
+	P_MII1_ETxEN, \
+	P_MII1_ERxD0, \
+	P_MII1_ERxD1, \
+	P_MII1_ERxER, \
+	P_MII1_TxCLK, \
+	P_MII1_PHYINT, \
+	P_MII1_CRS, \
+	P_MII1_MDC, \
+	P_MII1_MDIO, 0}
+
+/* PPI Port Mux */
+#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
+#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
+#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
+#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
+#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+#define P_PPI0_D16	(P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
+#define P_PPI0_D17	(P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
+#define P_PPI0_D18	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
+#define P_PPI0_D19	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
+#define P_PPI0_D20	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
+#define P_PPI0_D21	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
+#define P_PPI0_D22	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
+#define P_PPI0_D23	(P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
+#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
+#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
+#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
+#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
+
+#define P_PPI1_D0	(P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
+#define P_PPI1_D1	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
+#define P_PPI1_D2	(P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
+#define P_PPI1_D3	(P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
+#define P_PPI1_D4	(P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
+#define P_PPI1_D5	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
+#define P_PPI1_D6	(P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
+#define P_PPI1_D7	(P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
+#define P_PPI1_D8	(P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
+#define P_PPI1_D9	(P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
+#define P_PPI1_D10	(P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
+#define P_PPI1_D11	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
+#define P_PPI1_D12	(P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
+#define P_PPI1_D13	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
+#define P_PPI1_D14	(P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
+#define P_PPI1_D15	(P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
+#define P_PPI1_D16	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
+#define P_PPI1_D17	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
+#define P_PPI1_CLK	(P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
+#define P_PPI1_FS1	(P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
+#define P_PPI1_FS2	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
+#define P_PPI1_FS3	(P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
+
+#define P_PPI2_D0	(P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
+#define P_PPI2_D1	(P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
+#define P_PPI2_D2	(P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
+#define P_PPI2_D3	(P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
+#define P_PPI2_D4	(P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
+#define P_PPI2_D5	(P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
+#define P_PPI2_D6	(P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
+#define P_PPI2_D7	(P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
+#define P_PPI2_D8	(P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
+#define P_PPI2_D9	(P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
+#define P_PPI2_D10	(P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
+#define P_PPI2_D11	(P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
+#define P_PPI2_D12	(P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
+#define P_PPI2_D13	(P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
+#define P_PPI2_D14	(P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
+#define P_PPI2_D15	(P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
+#define P_PPI2_D16	(P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
+#define P_PPI2_D17	(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
+#define P_PPI2_CLK	(P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
+#define P_PPI2_FS1	(P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
+#define P_PPI2_FS2	(P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
+#define P_PPI2_FS3	(P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
+
+/* SPI Port Mux */
+#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
+#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
+#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
+#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
+#define P_SPI0_RDY	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
+#define P_SPI0_D2	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
+#define P_SPI0_D3	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
+
+#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
+#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
+#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
+#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
+#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
+#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
+#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
+
+#define P_SPI1_SS	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
+#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
+#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
+#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
+#define P_SPI1_RDY	(P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
+#define P_SPI1_D2	(P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
+#define P_SPI1_D3	(P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
+
+#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
+#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
+#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
+#define P_SPI1_SSEL4	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
+#define P_SPI1_SSEL5	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_SPI1_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_SPI1_SSEL7	(P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
+
+#define GPIO_DEFAULT_BOOT_SPI_CS
+#define P_DEFAULT_BOOT_SPI_CS
+
+/* UART Port Mux */
+#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
+#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
+#define P_UART0_RTS	(P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
+#define P_UART0_CTS	(P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
+
+#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+#define P_UART1_RTS	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+#define P_UART1_CTS	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+
+/* Timer */
+#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
+#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
+#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
+#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
+#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
+#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
+#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
+
+/* RSI */
+#define P_RSI_DATA0	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
+#define P_RSI_DATA1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#define P_RSI_DATA2	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
+#define P_RSI_DATA3	(P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
+#define P_RSI_DATA4	(P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
+#define P_RSI_DATA5	(P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
+#define P_RSI_DATA6	(P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
+#define P_RSI_DATA7	(P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
+#define P_RSI_CMD	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_RSI_CLK	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+
+/* PTP */
+#define P_PTP0_PPS	(P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
+#define P_PTP0_CLKIN	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
+#define P_PTP0_AUXIN	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
+
+#define P_PTP1_PPS	(P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
+#define P_PTP1_CLKIN	(P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
+#define P_PTP1_AUXIN	(P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
+
+/* SMC Port Mux */
+#define P_A3		(P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
+#define P_A4		(P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
+#define P_A5		(P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
+#define P_A6		(P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
+#define P_A7		(P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
+#define P_A8		(P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
+#define P_A9		(P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
+#define P_A10		(P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
+#define P_A11		(P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
+#define P_A12		(P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
+#define P_A13		(P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
+#define P_A14		(P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
+#define P_A15		(P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
+#define P_A16		(P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
+#define P_A17		(P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
+#define P_A18		(P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
+#define P_A19		(P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
+#define P_A20		(P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
+#define P_A21		(P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
+#define P_A22		(P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
+#define P_A23		(P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
+#define P_A24		(P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
+#define P_A25		(P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
+#define P_NORCK         (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
+
+#define P_AMS1		(P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
+#define P_AMS2		(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
+#define P_AMS3		(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
+
+#define P_ABE0		(P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(1))
+#define P_ABE1		(P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(1))
+
+/* CAN */
+#define P_CAN0_TX	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+#define P_CAN0_RX	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
+
+#endif				/* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/include/asm/mach-bf609/ports.h b/arch/blackfin/include/asm/mach-bf609/ports.h
new file mode 100644
index 0000000..b361c7b
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-bf609/ports.h
@@ -0,0 +1,103 @@ 
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+/* PORTx_MUX Masks */
+#define PORT_x_MUX_0_MASK	0x00000003
+#define PORT_x_MUX_1_MASK	0x0000000C
+#define PORT_x_MUX_2_MASK	0x00000030
+#define PORT_x_MUX_3_MASK	0x000000C0
+#define PORT_x_MUX_4_MASK	0x00000300
+#define PORT_x_MUX_5_MASK	0x00000C00
+#define PORT_x_MUX_6_MASK	0x00003000
+#define PORT_x_MUX_7_MASK	0x0000C000
+#define PORT_x_MUX_8_MASK	0x00030000
+#define PORT_x_MUX_9_MASK	0x000C0000
+#define PORT_x_MUX_10_MASK	0x00300000
+#define PORT_x_MUX_11_MASK	0x00C00000
+#define PORT_x_MUX_12_MASK	0x03000000
+#define PORT_x_MUX_13_MASK	0x0C000000
+#define PORT_x_MUX_14_MASK	0x30000000
+#define PORT_x_MUX_15_MASK	0xC0000000
+
+#define PORT_x_MUX_FUNC_1	(0x0)
+#define PORT_x_MUX_FUNC_2	(0x1)
+#define PORT_x_MUX_FUNC_3	(0x2)
+#define PORT_x_MUX_FUNC_4	(0x3)
+#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
+#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
+#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
+#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
+#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
+#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
+#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
+#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
+#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
+#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
+#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
+#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
+#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
+#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
+#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
+#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
+#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
+#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
+#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
+#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
+#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
+#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
+#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
+#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
+#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
+#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
+#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
+#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
+#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_8_FUNC_1	(PORT_x_MUX_FUNC_1 << 16)
+#define PORT_x_MUX_8_FUNC_2	(PORT_x_MUX_FUNC_2 << 16)
+#define PORT_x_MUX_8_FUNC_3	(PORT_x_MUX_FUNC_3 << 16)
+#define PORT_x_MUX_8_FUNC_4	(PORT_x_MUX_FUNC_4 << 16)
+#define PORT_x_MUX_9_FUNC_1	(PORT_x_MUX_FUNC_1 << 18)
+#define PORT_x_MUX_9_FUNC_2	(PORT_x_MUX_FUNC_2 << 18)
+#define PORT_x_MUX_9_FUNC_3	(PORT_x_MUX_FUNC_3 << 18)
+#define PORT_x_MUX_9_FUNC_4	(PORT_x_MUX_FUNC_4 << 18)
+#define PORT_x_MUX_10_FUNC_1	(PORT_x_MUX_FUNC_1 << 20)
+#define PORT_x_MUX_10_FUNC_2	(PORT_x_MUX_FUNC_2 << 20)
+#define PORT_x_MUX_10_FUNC_3	(PORT_x_MUX_FUNC_3 << 20)
+#define PORT_x_MUX_10_FUNC_4	(PORT_x_MUX_FUNC_4 << 20)
+#define PORT_x_MUX_11_FUNC_1	(PORT_x_MUX_FUNC_1 << 22)
+#define PORT_x_MUX_11_FUNC_2	(PORT_x_MUX_FUNC_2 << 22)
+#define PORT_x_MUX_11_FUNC_3	(PORT_x_MUX_FUNC_3 << 22)
+#define PORT_x_MUX_11_FUNC_4	(PORT_x_MUX_FUNC_4 << 22)
+#define PORT_x_MUX_12_FUNC_1	(PORT_x_MUX_FUNC_1 << 24)
+#define PORT_x_MUX_12_FUNC_2	(PORT_x_MUX_FUNC_2 << 24)
+#define PORT_x_MUX_12_FUNC_3	(PORT_x_MUX_FUNC_3 << 24)
+#define PORT_x_MUX_12_FUNC_4	(PORT_x_MUX_FUNC_4 << 24)
+#define PORT_x_MUX_13_FUNC_1	(PORT_x_MUX_FUNC_1 << 26)
+#define PORT_x_MUX_13_FUNC_2	(PORT_x_MUX_FUNC_2 << 26)
+#define PORT_x_MUX_13_FUNC_3	(PORT_x_MUX_FUNC_3 << 26)
+#define PORT_x_MUX_13_FUNC_4	(PORT_x_MUX_FUNC_4 << 26)
+#define PORT_x_MUX_14_FUNC_1	(PORT_x_MUX_FUNC_1 << 28)
+#define PORT_x_MUX_14_FUNC_2	(PORT_x_MUX_FUNC_2 << 28)
+#define PORT_x_MUX_14_FUNC_3	(PORT_x_MUX_FUNC_3 << 28)
+#define PORT_x_MUX_14_FUNC_4	(PORT_x_MUX_FUNC_4 << 28)
+#define PORT_x_MUX_15_FUNC_1	(PORT_x_MUX_FUNC_1 << 30)
+#define PORT_x_MUX_15_FUNC_2	(PORT_x_MUX_FUNC_2 << 30)
+#define PORT_x_MUX_15_FUNC_3	(PORT_x_MUX_FUNC_3 << 30)
+#define PORT_x_MUX_15_FUNC_4	(PORT_x_MUX_FUNC_4 << 30)
+
+#include "../mach-common/bits/ports-a.h"
+#include "../mach-common/bits/ports-b.h"
+#include "../mach-common/bits/ports-c.h"
+#include "../mach-common/bits/ports-d.h"
+#include "../mach-common/bits/ports-e.h"
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/cgu.h b/arch/blackfin/include/asm/mach-common/bits/cgu.h
new file mode 100644
index 0000000..cdf7349
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/cgu.h
@@ -0,0 +1,80 @@ 
+/*
+ * CGU Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_CGU__
+#define __BFIN_PERIPHERAL_CGU__
+
+/* CGU_CTL Masks */
+#define DF			(1 << 0)
+#define MSEL			(0x7f << MSEL_P)
+#define WIDLE			(1 << WIDLE_P)
+#define LOCK			(1 << LOCK_P)
+
+#define DF_P			0
+#define MSEL_P			8
+#define WIDLE_P			30
+#define LOCK_P			31
+#define MSEL_MASK               0x7F00
+#define DF_MASK                 0x1
+
+/* CGU_STAT Masks */
+#define PLLEN			(1 << 0)
+#define PLLBP			(1 << 1)
+#define PLLLK			(1 << 2)
+#define CLKSALGN		(1 << 3)
+#define CCBF0EN			(1 << 4)
+#define CCBF1EN			(1 << 5)
+#define SCBF0EN			(1 << 6)
+#define SCBF1EN			(1 << 7)
+#define DCBFEN			(1 << 8)
+#define OCBFEN			(1 << 9)
+#define ADRERR			(1 << 16)
+#define LWERR			(1 << 17)
+#define DIVERR			(1 << 18)
+#define WDFMSERR		(1 << 19)
+#define WDIVERR			(1 << 20)
+#define PLLLKERR		(1 << 21)
+
+/* CGU_DIV Masks */
+#define CSEL			(0x1f << CSEL_P)
+#define S0SEL			(3 << S0SEL_P)
+#define SYSSEL			(0x1f << SYSSEL_P)
+#define S1SEL			(3 << S1SEL_P)
+#define DSEL			(0x1f << DSEL_P)
+#define OSEL			(0x7f << OSEL_P)
+#define ALGN			(1 << ALGN_P)
+#define UPDT			(1 << UPDT_P)
+#define LOCK			(1 << LOCK_P)
+
+#define CSEL_P			0
+#define S0SEL_P			5
+#define SYSSEL_P		8
+#define S1SEL_P			13
+#define DSEL_P			16
+#define OSEL_P			22
+#define ALGN_P			29
+#define UPDT_P			30
+#define LOCK_P			31
+
+/* CGU_CLKOUTSEL Masks */
+#define CLKOUTSEL		(0xf << 0)
+#define USBCLKSEL		(0x3f << 16)
+#define LOCK			(1 << LOCK_P)
+
+#define LOCK_P			31
+
+#define CLKOUTSEL_CLKIN		0x0
+#define CLKOUTSEL_CCLK		0x1
+#define CLKOUTSEL_SYSCLK	0x2
+#define CLKOUTSEL_SCLK0		0x3
+#define CLKOUTSEL_SCLK1		0x4
+#define CLKOUTSEL_DCLK		0x5
+#define CLKOUTSEL_USB_PLL	0x6
+#define CLKOUTSEL_OUTCLK	0x7
+#define CLKOUTSEL_USB_CLKIN	0x8
+#define CLKOUTSEL_WDOG		0x9
+#define CLKOUTSEL_PMON		0xA
+#define CLKOUTSEL_GND		0xB
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/dde.h b/arch/blackfin/include/asm/mach-common/bits/dde.h
new file mode 100644
index 0000000..f7b0bb9
--- /dev/null
+++ b/arch/blackfin/include/asm/mach-common/bits/dde.h
@@ -0,0 +1,88 @@ 
+/*
+ * Distributed DMA Engine (DDE) Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_DDE__
+#define __BFIN_PERIPHERAL_DDE__
+
+/* DMA_CONFIG Masks */
+#define DMAEN			(1 << DMAEN_P)	/* DMA Channel Enable */
+#define WNR			(1 << WNR_P)	/* Channel Direction (W/R*) */
+#define SYNC			(1 << SYNC_P)	/* Sync Work Unit Transitions */
+#define CADDR			(1 << CADDR_P)	/* Use Current Address */
+#define PSIZE			(7 << PSIZE_P)	/* Peripheral Word Size */
+#define PSIZE_1			(0 << PSIZE_P)
+#define PSIZE_2			(1 << PSIZE_P)
+#define PSIZE_4			(2 << PSIZE_P)
+#define PSIZE_8			(3 << PSIZE_P)
+#define MSIZE			(7 << MSIZE_P)	/* Memory Transfer Size */
+#define MSIZE_1			(0 << MSIZE_P)
+#define MSIZE_2			(1 << MSIZE_P)
+#define MSIZE_4			(2 << MSIZE_P)
+#define MSIZE_8			(3 << MSIZE_P)
+#define MSIZE_16		(4 << MSIZE_P)
+#define MSIZE_32		(5 << MSIZE_P)
+#define FLOW			(7 << FLOW_P)	/* Next Operation */
+#define FLOW_STOP		(0 << FLOW_P)	/* Stop Mode */
+#define FLOW_AUTO		(1 << FLOW_P)	/* Autobuffer Mode */
+#define FLOW_DSCL		(4 << FLOW_P)	/* Descriptor List */
+#define FLOW_DSCA		(5 << FLOW_P)	/* Descriptor Array */
+#define FLOW_DSDL		(6 << FLOW_P)	/* Descriptor On Demand List */
+#define FLOW_DSDA		(7 << FLOW_P)	/* Descriptor On Demand Array */
+#define NDSIZE			(7 << NDSIZE_P)	/* Next Descriptor Set Size */
+#define NDSIZE_1		(0 << NDSIZE_P)
+#define NDSIZE_2		(1 << NDSIZE_P)
+#define NDSIZE_3		(2 << NDSIZE_P)
+#define NDSIZE_4		(3 << NDSIZE_P)
+#define NDSIZE_5		(4 << NDSIZE_P)
+#define NDSIZE_6		(5 << NDSIZE_P)
+#define NDSIZE_7		(6 << NDSIZE_P)
+#define DI_EN_X                 (1 << INT_P)
+#define DI_EN_Y                 (2 << INT_P)
+#define DI_EN_P			(3 << INT_P)
+#define DI_EN			(DI_EN_X)
+#define DI_XCOUNT_EN            (1 << INT_P)    /* xcount expires interrupt */
+#define TRIG			(3 << TRIG_P)	/* Generate Trigger */
+#define TOVEN			(1 << TOVEN_P)
+#define DESCIDCPY		(1 << DESCIDCPY_P)
+#define TWOD			(1 << TWOD_P)
+#define PDRF			(1 << PDRF_P)
+
+#define DMAEN_P			0
+#define WNR_P			1
+#define SYNC_P			2
+#define CADDR_P			3
+#define PSIZE_P			4
+#define MSIZE_P			8
+#define FLOW_P			12
+#define TWAIT_P			15
+#define NDSIZE_P		16
+#define INT_P			20
+#define TRIG_P			22
+#define TOVEN_P			24
+#define DESCIDCPY_P		25
+#define TWOD_P			26
+#define PDRF_P			28
+
+/* DMA_STATUS Masks */
+#define DMA_DONE		(1 << DMA_DONE_P)	/* Work Unit/Row Done */
+#define DMA_ERR			(1 << DMA_ERR_P)	/* Error Interrupt */
+#define DMA_PIRQ		(1 << DMA_PIRQ_P)	/* Peri Intr Request */
+#define DMA_ERRC		(7 << DMA_ERRC_P)	/* Error Cause */
+#define DMA_RUN			(7 << DMA_RUN_P)	/* Run Status */
+#define DMA_PBWIDTH		(3 << DMA_PBWIDTH_P)	/* Peri Bus Width */
+#define DMA_MBWIDTH		(3 << DMA_MBWIDTH_P)	/* Memory Bus Width */
+#define DMA_FIFOFILL		(7 << DMA_FIFOFILL_P)	/* FIFO Fill Status */
+#define DMA_TWAIT		(1 << DMA_TWAIT_P)	/* Trigger Wait Stat */
+
+#define DMA_DONE_P		0
+#define DMA_ERR_P		1
+#define DMA_PIRQ_P		2
+#define DMA_ERRC_P		4
+#define DMA_RUN_P		8
+#define DMA_PBWIDTH_P		12
+#define DMA_MBWIDTH_P		14
+#define DMA_FIFOFILL_P		16
+#define DMA_TWAIT_P		20
+
+#endif
diff --git a/arch/blackfin/include/asm/mach-common/bits/mpu.h b/arch/blackfin/include/asm/mach-common/bits/mpu.h
index 39998f8..cfde236 100644
--- a/arch/blackfin/include/asm/mach-common/bits/mpu.h
+++ b/arch/blackfin/include/asm/mach-common/bits/mpu.h
@@ -70,7 +70,11 @@ 
 #define PAGE_SIZE_4KB		0x00010000	/* 4 KB page size */
 #define PAGE_SIZE_1MB		0x00020000	/* 1 MB page size */
 #define PAGE_SIZE_4MB		0x00030000	/* 4 MB page size */
-#define PAGE_SIZE_MASK		0x00030000	/* the bits for the page_size field */
+#define PAGE_SIZE_16KB		0x00040000	/* 16 KB page size */
+#define PAGE_SIZE_64KB		0x00050000	/* 64 KB page size */
+#define PAGE_SIZE_16MB		0x00060000	/* 16 MB page size */
+#define PAGE_SIZE_64MB		0x00070000	/* 64 MB page size */
+#define PAGE_SIZE_MASK		0x00070000	/* page_size field mask */
 #define PAGE_SIZE_SHIFT		16
 #define CPLB_L1SRAM		0x00000020	/* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
 #define CPLB_PORTPRIO		0x00000200	/* 0=low priority port, 1= high priority port */
diff --git a/arch/blackfin/include/asm/mach-common/bits/pll.h b/arch/blackfin/include/asm/mach-common/bits/pll.h
index 9009f26..fe0ba0f 100644
--- a/arch/blackfin/include/asm/mach-common/bits/pll.h
+++ b/arch/blackfin/include/asm/mach-common/bits/pll.h
@@ -16,6 +16,8 @@ 
 #define MSEL			0x7E00		/* Multiplier Select For CCLK/VCO Factors */
 #define SPORT_HYST		0x8000		/* Enable Additional Hysteresis on SPORT Input Pins */
 
+#define MSEL_P			9
+
 /* PLL_DIV Masks */
 #define SSEL			0x000F		/* System Select */
 #define CSEL			0x0030		/* Core Select */
@@ -29,6 +31,9 @@ 
 #define CCLK_DIV4		CSEL_DIV4
 #define CCLK_DIV8		CSEL_DIV8
 
+#define SSEL_P			0
+#define CSEL_P			4
+
 /* PLL_STAT Masks */
 #define ACTIVE_PLLENABLED	0x0001		/* Processor In Active Mode With PLL Enabled */
 #define FULL_ON			0x0002		/* Processor In Full On Mode */