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[1/3] powerpc: Document FSL eSDHC bindings

Message ID 20090205190447.GA3348@oksana.dev.rtsoft.ru (mailing list archive)
State Accepted, archived
Commit 34bcda616e5308a0633d5bfabcc090d7aa09b494
Delegated to: Kumar Gala
Headers show

Commit Message

Anton Vorontsov Feb. 5, 2009, 7:04 p.m. UTC 
This patch documents OF bindings for the Freescale Enhanced Secure
Digital Host Controller.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 Documentation/powerpc/dts-bindings/fsl/esdhc.txt |   24 ++++++++++++++++++++++
 1 files changed, 24 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/powerpc/dts-bindings/fsl/esdhc.txt

Comments

Kumar Gala Feb. 6, 2009, 4:49 p.m. UTC | #1 
On Feb 5, 2009, at 1:04 PM, Anton Vorontsov wrote:

> This patch documents OF bindings for the Freescale Enhanced Secure
> Digital Host Controller.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
> Documentation/powerpc/dts-bindings/fsl/esdhc.txt |   24 +++++++++++++ 
> +++++++++
> 1 files changed, 24 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/powerpc/dts-bindings/fsl/esdhc.txt

applied to next

- k
diff mbox

Patch

diff --git a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
new file mode 100644
index 0000000..6008465
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
@@ -0,0 +1,24 @@ 
+* Freescale Enhanced Secure Digital Host Controller (eSDHC)
+
+The Enhanced Secure Digital Host Controller provides an interface
+for MMC, SD, and SDIO types of memory cards.
+
+Required properties:
+  - compatible : should be
+    "fsl,<chip>-esdhc", "fsl,mpc8379-esdhc" for MPC83xx processors.
+    "fsl,<chip>-esdhc", "fsl,mpc8536-esdhc" for MPC85xx processors.
+  - reg : should contain eSDHC registers location and length.
+  - interrupts : should contain eSDHC interrupt.
+  - interrupt-parent : interrupt source phandle.
+  - clock-frequency : specifies eSDHC base clock frequency.
+
+Example:
+
+sdhci@2e000 {
+	compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
+	reg = <0x2e000 0x1000>;
+	interrupts = <42 0x8>;
+	interrupt-parent = <&ipic>;
+	/* Filled in by U-Boot */
+	clock-frequency = <0>;
+};