From patchwork Mon Feb 18 20:21:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 221564 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E5D9C2C0099 for ; Tue, 19 Feb 2013 10:47:43 +1100 (EST) Received: from localhost ([::1]:34261 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U7XEN-0006jG-EJ for incoming@patchwork.ozlabs.org; Mon, 18 Feb 2013 15:22:31 -0500 Received: from eggs.gnu.org ([208.118.235.92]:38085) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U7XDn-0005al-DK for qemu-devel@nongnu.org; Mon, 18 Feb 2013 15:21:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U7XDg-00028D-ET for qemu-devel@nongnu.org; Mon, 18 Feb 2013 15:21:55 -0500 Received: from mail-pb0-f52.google.com ([209.85.160.52]:35500) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U7XDg-00027u-5s for qemu-devel@nongnu.org; Mon, 18 Feb 2013 15:21:48 -0500 Received: by mail-pb0-f52.google.com with SMTP id ma3so1819696pbc.11 for ; Mon, 18 Feb 2013 12:21:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=ucgDZ51PtBmtK+ZPJn1Cv6Jb3EwKzCNN92PxMd0gKuk=; b=Ns3nEJQ9pTfVMbOnTIyd0jl0REbz7nKqzFaouzUdAEhXsw75ovMx9VvA4TvvLrjfCY lIUbksMaqhd35LNyhnCxvF4R9bHL3e3cIPXEJArSVOE56A0ZWIk4pQPV5DVZbqTUevId TKRJ4WR81NhNQt/yi98YyP8cJWEz/R4iYYqkpXPTL68+jgNBkhIb5YTlDGDixWuj75W2 fcvXwW337FWuIOjIGGq3EpmZIvUD9F9jlBrKq6oMrOx0eFTZ3C7DG9o7Po/oxmloC/hU VRT3YtvINQM8qNIYIwl78oF/TWnLP0D/HUGaB2GAX3said/t3M0ea10WcS/AEI/AHw8j zF6A== X-Received: by 10.68.48.165 with SMTP id m5mr33863028pbn.40.1361218907498; Mon, 18 Feb 2013 12:21:47 -0800 (PST) Received: from pebble.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id z6sm78739077pav.3.2013.02.18.12.21.45 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 18 Feb 2013 12:21:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Feb 2013 12:21:07 -0800 Message-Id: <1361218873-1754-19-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1361218873-1754-1-git-send-email-rth@twiddle.net> References: <1361218873-1754-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.160.52 Cc: av1474@comtv.ru Subject: [Qemu-devel] [PATCH 18/24] tcg-ppc64: Implement compound logicals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Mostly copied from the ppc32 port. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 34 ++++++++++++++++++++++++++++++++++ tcg/ppc64/tcg-target.h | 20 ++++++++++---------- 2 files changed, 44 insertions(+), 10 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 576effc..a1be15a 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -385,6 +385,10 @@ static int tcg_target_const_match (tcg_target_long val, #define NOR XO31(124) #define CNTLZW XO31( 26) #define CNTLZD XO31( 58) +#define ANDC XO31( 60) +#define ORC XO31(412) +#define EQV XO31(284) +#define NAND XO31(476) #define MULLD XO31(233) #define MULHD XO31( 73) @@ -1415,6 +1419,26 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out32(s, XOR | SAB(a1, a0, a2)); } break; + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: + tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_nand_i32: + case INDEX_op_nand_i64: + tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); + break; + case INDEX_op_nor_i32: + case INDEX_op_nor_i64: + tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); + break; case INDEX_op_mul_i32: if (const_args[2]) { @@ -1788,6 +1812,11 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_and_i32, { "r", "r", "ri" } }, { INDEX_op_or_i32, { "r", "r", "ri" } }, { INDEX_op_xor_i32, { "r", "r", "ri" } }, + { INDEX_op_andc_i32, { "r", "r", "r" } }, + { INDEX_op_orc_i32, { "r", "r", "r" } }, + { INDEX_op_eqv_i32, { "r", "r", "r" } }, + { INDEX_op_nand_i32, { "r", "r", "r" } }, + { INDEX_op_nor_i32, { "r", "r", "r" } }, { INDEX_op_shl_i32, { "r", "r", "ri" } }, { INDEX_op_shr_i32, { "r", "r", "ri" } }, @@ -1806,6 +1835,11 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_and_i64, { "r", "r", "rU" } }, { INDEX_op_or_i64, { "r", "r", "rU" } }, { INDEX_op_xor_i64, { "r", "r", "rU" } }, + { INDEX_op_andc_i64, { "r", "r", "r" } }, + { INDEX_op_orc_i64, { "r", "r", "r" } }, + { INDEX_op_eqv_i64, { "r", "r", "r" } }, + { INDEX_op_nand_i64, { "r", "r", "r" } }, + { INDEX_op_nor_i64, { "r", "r", "r" } }, { INDEX_op_shl_i64, { "r", "r", "ri" } }, { INDEX_op_shr_i64, { "r", "r", "ri" } }, diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index f283dc8..a8cf4f0 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -82,11 +82,11 @@ typedef enum { #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_neg_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 -#define TCG_TARGET_HAS_orc_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 -#define TCG_TARGET_HAS_nand_i32 0 -#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_andc_i32 1 +#define TCG_TARGET_HAS_orc_i32 1 +#define TCG_TARGET_HAS_eqv_i32 1 +#define TCG_TARGET_HAS_nand_i32 1 +#define TCG_TARGET_HAS_nor_i32 1 #define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_movcond_i32 0 @@ -101,11 +101,11 @@ typedef enum { #define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_neg_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_orc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 -#define TCG_TARGET_HAS_nand_i64 0 -#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_orc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 1 +#define TCG_TARGET_HAS_nand_i64 1 +#define TCG_TARGET_HAS_nor_i64 1 #define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_movcond_i64 0