From patchwork Mon Feb 18 20:21:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 221497 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4F4412C007A for ; Tue, 19 Feb 2013 08:02:17 +1100 (EST) Received: from localhost ([::1]:34273 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U7XEW-0006jg-GM for incoming@patchwork.ozlabs.org; Mon, 18 Feb 2013 15:22:40 -0500 Received: from eggs.gnu.org ([208.118.235.92]:38093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U7XDo-0005cx-0I for qemu-devel@nongnu.org; Mon, 18 Feb 2013 15:22:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1U7XDk-00029r-02 for qemu-devel@nongnu.org; Mon, 18 Feb 2013 15:21:55 -0500 Received: from mail-da0-f41.google.com ([209.85.210.41]:53512) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1U7XDj-00028s-R6 for qemu-devel@nongnu.org; Mon, 18 Feb 2013 15:21:51 -0500 Received: by mail-da0-f41.google.com with SMTP id e20so2611191dak.14 for ; Mon, 18 Feb 2013 12:21:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:sender:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references; bh=9H3qpYtoGrM+JxtZbkmnxoCKq51hG5AUrt1EZpz+ODA=; b=gS2EjLmNznbhYHrQQFhu2FLfHgg1zhvvkJaqs5iKUxA11nRkrggA9P89IRSNKcvIv2 Vh/g5ju/qzZumMEvkPOnrADKORfjDLVBF85UAAkUrfko/frZ+DmDKLtT7KqA4wC0pDYv Bqb1CEiWQjHHsynkZUdAcaSquM10npbsxsgGp4Bjquz/CB6s+rnH5JPthdWlKgpfLE+N dWCbFXjyZhqmGf25qKQKGSqdjA0ovPQ71Q7JYVZ6LkSBteC+JhQSDeJhwVaqzt+w5qbD 5RCjOFMARl5ruFcd5heZs3qn4UKOEqwCDyhfgHsN9jVMfdXU+fxMH6rj2SYUbDhSwFee QEzQ== X-Received: by 10.68.233.71 with SMTP id tu7mr33420848pbc.119.1361218910723; Mon, 18 Feb 2013 12:21:50 -0800 (PST) Received: from pebble.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id z6sm78739077pav.3.2013.02.18.12.21.49 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 18 Feb 2013 12:21:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Feb 2013 12:21:09 -0800 Message-Id: <1361218873-1754-21-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1361218873-1754-1-git-send-email-rth@twiddle.net> References: <1361218873-1754-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 209.85.210.41 Cc: av1474@comtv.ru Subject: [Qemu-devel] [PATCH 20/24] tcg-ppc64: Use I constraint for mul X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The mul_i32 pattern was loading non-16-bit constants into a register, when we can get the middle-end to do that for us. The mul_i64 pattern was not considering that MULLI takes 64-bit inputs. Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 2b9309d..c866e4f 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1441,17 +1441,12 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_mul_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { - if (args[2] == (int16_t) args[2]) - tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1]) - | (args[2] & 0xffff)); - else { - tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]); - tcg_out32 (s, MULLW | TAB (args[0], args[1], 0)); - } + tcg_out32(s, MULLI | TAI(a0, a1, a2)); + } else { + tcg_out32(s, MULLW | TAB(a0, a1, a2)); } - else - tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2])); break; case INDEX_op_div_i32: @@ -1610,7 +1605,12 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_mul_i64: - tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2])); + a0 = args[0], a1 = args[1], a2 = args[2]; + if (const_args[2]) { + tcg_out32(s, MULLI | TAI(a0, a1, a2)); + } else { + tcg_out32(s, MULLD | TAB(a0, a1, a2)); + } break; case INDEX_op_div_i64: tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2])); @@ -1812,7 +1812,7 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_ld32s_i64, { "r", "r" } }, { INDEX_op_add_i32, { "r", "r", "ri" } }, - { INDEX_op_mul_i32, { "r", "r", "ri" } }, + { INDEX_op_mul_i32, { "r", "r", "rI" } }, { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, { INDEX_op_rem_i32, { "r", "r", "r" } }, @@ -1856,7 +1856,7 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_rotl_i64, { "r", "r", "ri" } }, { INDEX_op_rotr_i64, { "r", "r", "ri" } }, - { INDEX_op_mul_i64, { "r", "r", "r" } }, + { INDEX_op_mul_i64, { "r", "r", "rI" } }, { INDEX_op_div_i64, { "r", "r", "r" } }, { INDEX_op_divu_i64, { "r", "r", "r" } }, { INDEX_op_rem_i64, { "r", "r", "r" } },